Copper Interconnect Grain Boundary Blocking for Electromigration
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Solution Overview
Problem
In semiconductor processing, the increasing complexity and miniaturization of integrated circuits lead to challenges in reducing electromigration and stress voids in metal interconnect structures, particularly in submicron-sized, low resistance-capacitance (RC) metallization patterns, where conventional methods fail to adequately address the limitations imposed by interconnection capacitance and manufacturing throughput.
Innovation Solution
A method involving the implantation of alloying elements into the interconnect structure, followed by annealing, to form a doped region with blocked grain boundaries, which reduces electromigration and stress by using a barrier layer as an implant block to prevent alloying elements from entering the dielectric layer, and subsequently forming a copper interconnect with a doped top portion to enhance electromigration resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional copper interconnect structures are used in submicron technologies, then low resistance and high conductivity are achieved, but electromigration and stress voids occur reducing reliability
Solution Approach 1:
The patent applies local quality by creating a doped region only in the top portion of the copper interconnect rather than doping the entire structure. This localized doping approach blocks grain boundaries at the critical top surface where electromigration occurs most severely, while maintaining the bulk copper's excellent electrical conductivity. The selective implantation of alloying elements (such as Si, B, P, or C) into the top 10-50 nm of the copper interconnect provides targeted electromigration resistance without compromising overall device performance
Solution Approach 2:
The patent creates a composite interconnect structure consisting of undoped copper bulk material combined with a doped top region containing copper and alloying elements. This composite structure leverages the high conductivity of pure copper in the bulk while utilizing the electromigration-resistant properties of the doped surface layer. The combination of different material properties in specific locations optimizes both electrical performance and reliability
2Reliability
If alloying elements are implanted throughout the entire interconnect, then electromigration resistance improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the interconnect into two distinct regions: a doped top portion and an undoped bulk portion. This segmentation is achieved through controlled ion implantation that affects only the top 10-50 nm of the copper interconnect. The segmented approach allows selective application of doping treatment where it is most needed (at the top surface exposed to electromigration stresses) while leaving the bulk material simple and easy to manufacture
Solution Approach 2:
The patent applies partial action by implanting alloying elements only to the extent necessary to form a thin doped layer at the top surface, rather than saturating the entire interconnect. The doping concentration and depth are carefully controlled to provide sufficient electromigration resistance without excessive manufacturing complexity. This partial treatment focuses resources on the critical failure zone rather than treating the entire structure uniformly
3Manufacturing precision
If ion implantation is performed without a barrier layer, then alloying elements penetrate the interconnect, but alloying elements also contaminate the dielectric layer
Solution Approach 1:
The patent introduces a barrier layer as an intermediary between the ion implantation source and the dielectric layer. This barrier layer selectively blocks alloying elements from penetrating into the dielectric while allowing controlled implantation into the copper interconnect. The barrier layer acts as a mediator that enables the desired doping of the interconnect while preventing the harmful contamination of adjacent dielectric structures
Solution Approach 2:
The patent applies preliminary anti-action by placing the barrier layer in position before ion implantation occurs. This pre-positioned barrier prevents the harmful effect of dielectric contamination from occurring in the first place, while still allowing the beneficial doping of the copper interconnect to proceed. The barrier layer is strategically positioned to counteract the potential harmful penetration of alloying elements into sensitive dielectric regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces electromigration and stress voids by blocking grain boundaries with alloying elements, thereby improving the reliability and performance of metal interconnects in high-density semiconductor devices, enhancing manufacturing efficiency and reducing manufacturing costs.
Implementation Method 1
implanting alloying elements into the interconnect to form a first implanted region in the interconnect
Implementation Method 2
annealing the interconnect and the first implanted region to form a first doped region in a top portion of the interconnect
Implementation Method 3
annealing the interconnect and the first implanted region to form a first doped region
Data Source
AI summary
Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.