Copper Interconnect Grain Growth for Resistivity Reduction
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Solution Overview
Problem
Copper interconnects in semiconductor devices exhibit increased electrical resistivity and susceptibility to electromigration as feature sizes decrease below 75 nm due to small grain sizes, and existing methods to promote grain growth can degrade dielectric material and create voids.
Innovation Solution
The method involves forming a copper layer with grains larger than 0.05 microns, annealing to grow a bamboo microstructure with perpendicular grain boundaries, and using a barrier layer to reduce electromigration, while avoiding damage to the dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper interconnect feature sizes are decreased to enable miniaturization, then circuit density and integration are improved, but electrical resistivity increases due to small grain sizes
Solution Approach 1:
The patent changes the grain size parameter of copper from sub-75nm to larger than 75nm through controlled grain growth processes, thereby reducing electrical resistivity while maintaining miniaturized interconnect dimensions. This parameter change directly addresses the contradiction by decoupling feature size from grain size.
Solution Approach 2:
The patent introduces grain growth promotion layers (such as ruthenium, rhodium, or iridium) as composite structures with copper interconnects. These layers promote grain growth and stabilize large grain structures, enabling low-resistivity copper interconnects at scaled dimensions.
2Reliability
If grain growth promotion layers are deposited to increase grain size, then electrical resistivity is reduced, but dielectric material functionality degrades resulting in leakage and increased k value
Solution Approach 1:
The patent uses grain growth promotion layers as intermediary materials between the copper interconnect and the dielectric material. These layers (ruthenium, rhodium, or iridium) mediate the grain growth process while protecting the dielectric material from degradation, thus resolving the contradiction between reducing resistivity and preventing dielectric damage.
Solution Approach 2:
The grain growth promotion layers are used as sacrificial or temporary structures that facilitate grain growth during manufacturing, then are removed or replaced. This allows the beneficial grain growth effect to be achieved without the permanent presence of materials that could degrade dielectric properties.
3Ease of manufacture
If conventional copper deposition processes are used, then manufacturing simplicity is maintained, but voids are created in lines and vias increasing electromigration susceptibility
Solution Approach 1:
The patent performs preliminary actions during copper deposition by controlling deposition parameters (such as sputtering power, gas flow rates, and substrate temperature) to ensure complete filling of vias and lines without void formation. This preliminary control of deposition conditions prevents void creation before electromigration becomes an issue, maintaining both manufacturing simplicity and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical resistivity and increases resistance to electromigration by forming copper interconnects with larger grains and a bamboo microstructure, enhancing the reliability of semiconductor devices without degrading the dielectric material.
Implementation Method 1
The copper layer is annealed and grains within the copper layer are grown to form a bamboo microstructure
Data Source
AI summary
Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.