Copper Interconnect Hard Mask Etching for Via Bridging
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating copper interconnects due to the lack of volatile copper compounds, which complicates patterning and diffusion through dielectric materials, and the reduction of dielectric constants in low-K dielectrics affects metallic interconnect fabrication.
Innovation Solution
A method involving multiple photoresist layers and etching processes is used to form metal features in metallization layers, including a hard mask layer etching process that widens via landing windows and trench openings, allowing for improved patterning and reduced leakage in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional photoresist masking and plasma etching are used for patterning, then aluminum interconnects can be successfully fabricated, but copper interconnects cannot be patterned due to lack of volatile copper compounds
Solution Approach 1:
The patent introduces a self-aligned mandrel and spacer structure as an intermediary patterning approach. Instead of relying on volatile copper compounds for direct etching, the method uses a sacrificial mandrel structure with spacers to define the final copper interconnect pattern. This intermediary patterning technique enables copper fabrication without requiring traditional photoresist-copper chemistry compatibility.
2Reliability
If copper is used for interconnects, then electrical conductivity and thermal conductivity are improved, but diffusion through dielectric materials complicates fabrication
Solution Approach 1:
The patent extracts the copper material from direct contact with dielectric layers by using a self-aligned patterning approach where copper is deposited only in defined regions bounded by spacers. This extraction of copper from potential diffusion zones eliminates the need for complex diffusion barriers while maintaining the electrical conductivity benefits of copper interconnects.
3Reliability
If low-K dielectrics are used to reduce dielectric constant, then device functionality is improved, but integration with metallic interconnects becomes more difficult
Solution Approach 1:
The patent segments the patterning process into distinct stages: mandrel formation, spacer deposition, and selective etching. This segmentation allows low-K dielectric materials to be integrated without requiring them to withstand harsh photoresist masking conditions, as the low-K dielectric is processed during the spacer formation and etching stages rather than during initial photoresist patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication of metallic interconnects in low-K dielectrics, improving device performance by maintaining effective material properties and reducing integration challenges.
Implementation Method 1
A method involving multiple photoresist layers and etching processes is used to form metal features in metallization layers
Data Source
AI summary
A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.