Copper Interconnect MnOx Capping for Lower RC Delay
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Solution Overview
Problem
The use of metals in copper interconnects for semiconductor devices leads to high resistance and increased RC delay due to diffusion and reaction with low-k dielectric materials, necessitating the formation of additional capping layers that increase capacitance.
Innovation Solution
A semiconductor device is developed with a manganese oxide (MnOx) layer formed on metallic patterns through separate two-times anneal processes, acting as a capping layer to reduce capacitance and eliminate the need for additional layers, thereby reducing resistance and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metals are used in copper interconnects to improve adhesion and reduce diffusion, then reliability is improved, but resistance increases and RC delay increases
Solution Approach 1:
The patent extracts and removes the metal layer from the interconnect structure through a selective removal process. The metal is eliminated while preserving the copper interconnect, thereby eliminating the harmful effects of metal-induced resistance and RC delay while maintaining the benefits of reduced diffusion through alternative means
Solution Approach 2:
The patent changes the compositional parameters of the interconnect structure by transitioning from a metal-containing composite material to a pure copper or copper-alloy interconnect. This parameter change eliminates the harmful electrical properties introduced by metal while maintaining structural integrity through controlled deposition and annealing processes
2Reliability
If additional capping layers are formed to prevent metal diffusion, then reliability is improved, but device complexity increases and capacitance increases
Solution Approach 1:
The patent removes the metal component that necessitates additional capping layers, thereby eliminating the need for complex multi-layer structures. The selective removal of metal simplifies the overall device architecture while maintaining diffusion prevention through the preserved copper structure and modified deposition processes
Solution Approach 2:
The patent makes the copper interconnect structure itself serve multiple functions: it provides both the conductive pathway and the diffusion barrier functionality that would otherwise require separate metal layers and capping layers. This multi-functionality reduces device complexity while maintaining reliability
3Reliability
If additional capping layers are formed to prevent metal diffusion, then reliability is improved, but capacitance increases and RC delay increases
Solution Approach 1:
The patent extracts and removes the metal layer that causes both the need for capping layers and the associated capacitance increase. By eliminating the metal, the patent removes the source of diffusion problems without adding the capacitance penalty of additional capping layers
Solution Approach 2:
The patent changes the material composition parameters to eliminate metal-containing compounds that would increase capacitance. The resulting pure copper or copper-alloy interconnect structure has lower capacitance and RC delay while maintaining diffusion prevention through controlled material deposition and thermal processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MnOx layer reduces capacitance by 5% to 10% and decreases the atomic percentage of manganese, leading to lower resistance and increased interconnect speed, enhancing electrical performance and reliability.
Implementation Method 1
a manganese oxide (MnOx) layer formed on metallic patterns through separate two-times anneal processes
Implementation Method 2
separate two-times anneal processes
Data Source
AI summary
A semiconductor structure includes an interconnect structure including a first metallic pattern and a metal oxide layer. The first metallic pattern is disposed in a first opening of a dielectric layer and includes a first barrier layer lining the first opening and a first conductive layer over the first barrier layer. A top surface of the first conductive layer is between a top surface and a bottom surface of the dielectric layer. The metal oxide layer is on the top surface of the first conductive layer, and a top surface of the metal oxide layer is substantially leveled with the top surface of the dielectric layer.