Copper Interconnection via Selective Etching of Cu3N Composite
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Solution Overview
Problem
The copper interconnection process in semiconductor manufacturing is costly and prone to defects due to the use of Chemical Mechanical Polish (CMP), which is expensive and can introduce defects on copper surfaces.
Innovation Solution
A method involving the deposition of a copper diffusion barrier layer and a copper composite layer, followed by decomposing the composite into copper at specific positions using techniques like annealing or electron beam bombardment, eliminating the need for CMP and forming spacers on the sidewalls to prevent copper diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Chemical Mechanical Polish (CMP) is used to planarize copper interconnection, then copper surface flatness is improved, but manufacturing cost increases and defects are introduced on copper surfaces
Solution Approach 1:
The patent extracts and removes the CMP process from the copper interconnection manufacturing flow. Instead of using CMP to planarize copper surfaces, the invention uses a copper composite layer that can be selectively etched away, eliminating the need for expensive CMP equipment and processes while avoiding CMP-induced defects on copper surfaces
Solution Approach 2:
The patent introduces a copper composite layer (such as Cu3N) that serves as a temporary, disposable structure. This composite layer is easily etched away by HF to reveal the underlying copper interconnection, replacing the need for expensive CMP processing. The copper composite acts as a sacrificial layer that is removed after serving its patterning function
2Manufacturing precision
If Chemical Mechanical Polish (CMP) is used to planarize copper interconnection, then copper surface flatness is improved, but manufacturing defects increase
Solution Approach 1:
The patent removes the CMP process from the manufacturing flow entirely. By using a copper composite layer that can be selectively etched, the invention avoids CMP-induced defects such as surface roughness, dishing, and contamination, while still achieving the necessary copper interconnection patterning and flatness through the etching process
3Ease of manufacture
If copper diffusion barrier layer and copper composite layer are deposited and then selectively etched, then manufacturing cost is reduced and defects are eliminated, but process complexity increases
Solution Approach 1:
The patent changes the chemical parameters of the copper layer by using a copper composite material (such as Cu3N) instead of pure copper. This parameter change enables selective etching with HF, which selectively removes the copper composite while leaving the copper diffusion barrier layer intact. The process complexity is managed through well-established deposition and etching techniques that are already part of standard semiconductor manufacturing
Solution Approach 2:
The patent uses a copper composite layer (Cu3N) combined with a copper diffusion barrier layer (TaN, TiN, Ta, Ti, TiSiN, TaSiN, TiW, WN, or Ru). This composite structure enables selective etching processes where the copper composite can be removed by HF while the diffusion barrier layer remains, providing a controlled way to form copper interconnections without requiring CMP
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and defects by eliminating the need for CMP, while ensuring effective electrical connectivity between semiconductor devices with spacers preventing copper diffusion.
Implementation Method 1
decomposing the copper composite at corresponding positions, where the copper interconnection is to be formed, into copper
Implementation Method 2
bombarding the Cu3N layer by an electron beam by using the patterned photoresist layer as a mask to decompose the Cu3N into copper
Implementation Method 3
depositing an oxide layer on the Cu3N layer
Implementation Method 4
applying a photoresist layer on the oxide layer, which is patterned according to the shape of the copper interconnection
Implementation Method 5
The Cu3N layer and the copper diffusion barrier layer are selectively etched by HF
Data Source
AI summary
The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.