Copper Mask Shallow Trench Isolation for Semiconductor Integration
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Solution Overview
Problem
The existing methods for forming shallow trench isolation (STI) in semiconductor devices face challenges in achieving highly integrated devices due to limitations in photolithography, which result in 'bird's beak' regions and difficulty in forming thin and deep trenches, hindering the insulation and integration of semiconductor elements.
Innovation Solution
A method using a copper layer as a mask in the STI process, where a photosensitive layer pattern is formed, planarized, and then removed, allowing for the etching of a trench with high selectivity to form a thinner and deeper trench, followed by trench oxide layer formation and planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a photosensitive layer pattern is used as a mask to form a trench in STI process, then the trench can be formed with defined dimensions, but the photolithography process limitations prevent forming trenches thinner than a predetermined width
Solution Approach 1:
A copper layer is introduced as an intermediary mask between the photosensitive layer and the substrate. The copper layer has superior etch selectivity compared to the photosensitive layer, enabling precise trench formation with dimensions below the photolithography resolution limit. The copper layer acts as a mediator that translates the larger photosensitive pattern into a finer trench structure.
Solution Approach 2:
The invention changes the material parameter of the mask from organic photosensitive material to metallic copper, which fundamentally alters the etch selectivity and resolution characteristics. This parameter change enables the formation of trenches with widths and depths that cannot be achieved using conventional photosensitive materials alone.
2Reliability
If a LOCOS type field oxide layer is used to electrically separate semiconductor elements, then the separation can be achieved, but 'bird's beak' regions are generated that allow semiconductor elements to partially invade active regions
Solution Approach 1:
The invention extracts and eliminates the problematic 'bird's beak' region by replacing the LOCOS oxidation process with a trench-based STI process. The trench is formed with vertical walls using the copper mask, and the oxide is deposited only within the trench, completely removing the gradual transition zone that characterizes LOCOS bird's beak regions.
Solution Approach 2:
Instead of forming the isolation layer by oxidizing the surface (LOCOS approach), the invention inverts the approach by first forming a trench and then filling it with oxide material (STI approach). This inversion eliminates the bird's beak formation mechanism entirely, as the oxide is confined to the trench region with sharp boundaries.
3Length of moving object
If the photosensitive layer pattern height is reduced to form thinner trenches, then the trench width can be reduced, but the etching selectivity and depth control become more difficult
Solution Approach 1:
The copper layer serves as an intermediary that decouples the relationship between photosensitive layer height and trench depth. The copper layer can be formed with precise thickness control through electroplating, and its high etch selectivity provides excellent depth control during trench etching, independent of the photosensitive layer dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thinner and deeper trenches, improving insulation and integration capabilities in semiconductor devices by utilizing the copper layer's high selectivity to reduce the photosensitive layer pattern height and width, thus enhancing the integration density of semiconductor devices.
Implementation Method 1
The copper layer is planarized using a CMP process until a surface of the photosensitive layer pattern is exposed
Implementation Method 2
The substrate is etched using the copper layer as a mask to form a trench
Implementation Method 3
The photosensitive layer pattern is removed through a wet etching process
Implementation Method 4
The copper layer may be formed using an electro-chemical plating (ECP) method
Implementation Method 5
a trench oxide layer 19 such as a CVD oxide using a TEOS oxidation film and a high density plasma CVD oxide is buried in the trench
Implementation Method 6
The trench oxide layer is planarized using the CMP process
Data Source
AI summary
A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined value due to limitations on the photolithography process.