Copper Metallization Stress Management via Segmented Barrier Layers
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Solution Overview
Problem
Copper metallization in semiconductor devices experiences stress-induced failures due to elastic and plastic deformation during temperature cycling, leading to issues like cracks and delamination, and has low routing density, increasing costs with additional layers.
Innovation Solution
A semiconductor device design featuring a barrier layer between the copper metallization and substrate, with a passivation layer interposed in specific regions to manage stress and routing, and a method of manufacturing that structures the barrier layer as a signal routing structure and washer-like structure to enhance routing density without additional layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper film is used as power metallization, then electrical conductivity is improved, but stress-induced failures occur due to elastic and plastic deformation during temperature cycling
Solution Approach 1:
The copper power metallization is divided into multiple segments separated by voids or trenches filled with dielectric material. This segmentation reduces the continuous stress path and prevents stress accumulation that leads to delamination and cracking during temperature cycling, while maintaining adequate electrical conductivity through the segmented structure.
Solution Approach 2:
The patent introduces regions with different morphologies - dense copper regions for electrical conductivity and void-filled regions for stress management. This local differentiation allows the structure to simultaneously achieve good electrical performance and stress resistance by placing each type of region where it is most needed.
2Power
If thick copper metallization is used, then current carrying capacity is improved, but routing density decreases due to low pitch
Solution Approach 1:
The patent utilizes vertical dimension by creating through-substrate vias and multi-layer copper structures connected by vertical interconnects. This allows routing to occur in multiple dimensions rather than being constrained to a single plane, effectively increasing routing density while maintaining thick copper for current carrying capacity.
Solution Approach 2:
The patent implements nested copper structures where thinner copper routing layers are positioned within or alongside thicker power copper layers. This nesting allows signal routing and power delivery to coexist in the same vertical space, increasing overall routing density without compromising the current carrying capacity of the thick copper layers.
3Productivity
If additional routing layers are added to increase routing density, then routing capacity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent designs copper structures that serve multiple functions simultaneously - thick copper layers provide both power delivery and signal routing capabilities, while void regions serve both stress management and insulation functions. This multi-functionality reduces the need for separate dedicated layers, simplifying manufacturing while maintaining high routing density.
Solution Approach 2:
The patent merges power delivery and signal routing functions into the same copper structure where possible. By allowing thick copper layers to perform both power and signal functions, and by integrating stress management features into the routing structure itself, the patent reduces the total number of separate layers and processes required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates stress-induced failures and increases routing density in semiconductor devices, reducing costs and complexity by integrating stress management and routing enhancements within the existing copper metallization structure.
Implementation Method 1
a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate
Implementation Method 2
when a copper film is subjected to temperature cycling, the copper film undergoes elastic and plastic deformation which induces stress on the surrounding elements such as the barrier, ILD (interlayer dielectric), passivation, etc.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.