Copper Pad Passivation Structure With Stress Buffer Layer
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable devices at increasingly smaller sizes, as the complexity of processing and manufacturing increases due to decreasing feature sizes, leading to difficulties in forming reliable semiconductor devices.
Innovation Solution
A method involving the formation of a semiconductor device with a stress buffer layer between passivation layers to absorb stress from thick copper pad structures, preventing crack and delamination issues, and enhancing the reliability of the semiconductor device by using a stacked structure of a first passivation layer, a stress buffer layer, and a second passivation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases and manufacturing reliability deteriorates
Solution Approach 1:
The patent segments the passivation structure into multiple layers (first passivation layer, second passivation layer) with a stress buffer layer in between. This segmentation allows each layer to perform specific functions: the outer passivation layers provide protection while the intermediate stress buffer layer specifically manages stress, thereby maintaining reliability despite continued scaling for higher productivity.
Solution Approach 2:
The stress buffer layer acts as an intermediary between the copper pad structure and the passivation layers. It mediates the stress interaction by absorbing expansion forces, preventing direct transmission of stress to the passivation layers and underlying structures, thus maintaining manufacturing reliability during continued feature size reduction.
2Reliability
If copper pad structures are made thicker to improve electrical performance, then electrical conductivity improves, but stress and risk of crack and delamination increase
Solution Approach 1:
The patent converts the harmful stress generated by thick copper pad expansion into a beneficial outcome by introducing the stress buffer layer. This layer absorbs the expansion stress, transforming what would be a harmful force causing delamination into a contained energy dissipation mechanism, thereby allowing thick copper pads to maintain both electrical performance and mechanical integrity.
Solution Approach 2:
The patent changes the mechanical parameters of the structure by introducing a layer with specific stress-absorbing properties. The stress buffer layer has tailored material parameters that allow it to accommodate copper expansion, effectively changing the overall stress distribution parameters of the pad structure system and preventing failure modes.
3Reliability
If a stacked structure with stress buffer layer is used to absorb stress, then crack and delamination are prevented, but device complexity increases
Solution Approach 1:
The passivation structure is segmented into functional layers with the stress buffer layer positioned strategically between the copper pad and outer passivation layers. This segmentation creates a specialized stress management zone without requiring complete restructuring of the entire device, thereby limiting the increase in complexity to only the necessary functional addition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress buffer layer effectively absorbs stress from thick copper pad structures, improving the reliability of semiconductor devices by preventing crack and delamination issues, thus ensuring better mechanical strength and contact area.
Implementation Method 1
a stress buffer layer between a first passivation layer and a second passivation layer. The stress buffer layer may have a Young's modulus less than a Young's modulus of the first passivation layer and a Young's modulus of the second passivation layer
Data Source
AI summary
Provided is a semiconductor device including a substrate, an interconnect structure, a first passivation layer, a stress buffer layer, a pad structure, and a second passivation layer. The interconnect structure is disposed on the substrate. The first passivation layer and the stress buffer layer are disposed on the interconnect structure. The pad structure includes: a lower portion embedded in the first passivation layer and the stress buffer layer, and laterally wrapped by the first passivation layer and the stress buffer layer; and an upper portion on the lower portion. The upper portion has a periphery laterally offset outward from a periphery of the lower portion, so that a bottom surface of the upper portion contacts a top surface of the stress buffer layer. The second passivation layer is disposed on the stress buffer layer and laterally wraps the upper portion of the upper portion of the pad structure.