Copper-Phosphorous Wiring Structure for Void-Free Via Filling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional copper sputtering methods for fabricating semiconductor devices and printed circuit boards face issues such as defects in advanced technology nodes, particularly with high aspect ratio vias, where the deposited material can stick at openings, forming voids and causing reliability problems.
Innovation Solution
The use of a copper-phosphorous alloy, specifically copper(I) phosphide (Cu3P), which offers improved anti-corrosive, wear-resistant, and conformable properties, is introduced as a replacement for sputtered copper, allowing for better wetting and barrier layer performance without the need for high-temperature annealing, and can be formed through electroless or electroplating operations at lower temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper sputtering is used to fabricate conductive structures, then electrical conductivity is achieved, but voids form in high aspect ratio vias reducing reliability
Solution Approach 1:
The patent changes the material parameter from pure copper to copper-phosphorous alloy (Cu3P), which fundamentally alters the deposition characteristics. This alloy enables conformal deposition in high aspect ratio vias without void formation, directly resolving the reliability issue while maintaining manufacturing precision
Solution Approach 2:
The patent employs a composite material system consisting of copper-phosphorous alloy combined with barrier layers (taconol, tantalum nitride, or tungsten). This composite approach leverages the superior wetting properties of Cu3P to achieve void-free via filling while the barrier layers prevent copper diffusion, simultaneously improving both reliability and manufacturing precision
2Strength
If conventional copper structures are used, then processing is simpler, but wear resistance and anti-corrosion performance are insufficient
Solution Approach 1:
The patent creates a multi-layer composite structure with copper-phosphorous alloy as the conductive component and barrier layers (taconol, tantalum nitride, or tungsten) as protective components. This composite design enhances wear resistance and anti-corrosion performance while managing the increased material complexity through systematic layer integration
Solution Approach 2:
The patent applies different material properties to different locations: the copper-phosphorous alloy provides conductivity and wear resistance in the via regions, while the barrier layers provide corrosion protection at the interface with dielectric materials. This localized quality assignment optimizes both strength and manages device complexity
3Reliability
If copper-phosphorous alloy is used, then wetting and barrier layer performance improve, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary surface preparation including surface treatment and activation steps before plating the copper-phosphorous alloy. This preliminary action ensures optimal surface conditions for the alloy deposition, improving adhesion reliability while managing manufacturing complexity through standardized pre-treatment procedures
Solution Approach 2:
The patent utilizes electroless plating parameters (temperature, pH, chemical composition) to achieve conformal deposition of copper-phosphorous alloy with controlled thickness and composition. By optimizing these parameters, the process achieves improved wetting and adhesion while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The copper-phosphorous alloy enhances the reliability and conductivity of semiconductor devices and printed circuit boards by reducing void formation, improving wear resistance, and maintaining electrical and thermal conductivity comparable to sputtered copper, while being compatible with advanced technology nodes and extreme environments.
Implementation Method 1
can be formed through electroless or electroplating operations at lower temperatures
Implementation Method 2
can be formed through electroless or electroplating operations at lower temperatures
Data Source
AI summary
The present disclosure provides a multilayer wiring structure, including a plurality of dielectric layers, a plurality of conductive wiring layers interleaved with the plurality of dielectric layers, wherein the plurality of conductive wiring layers includes copper-phosphorous alloys (such as Cu3P).