Copper Pillar Attach Substrate with Segmented Traces
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Solution Overview
Problem
The manufacturing tolerances of flipchip die mount substrates are very small, leading to potential failures such as short circuits, solder resist undercut, and alignment issues during the bonding process of copper pillars with solder tips, which are costly to optimize and affect product yield.
Innovation Solution
A CuP attach substrate design with a dielectric layer and solder resist layer having conductive coating layers on intermediate portions of traces, raising the effective contact surface above the solder resist layer, allowing for larger CuP diameters and reduced precision in alignment, and staggered trace ends to minimize overlap and shorts, thereby preventing solder resist undercut and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional contact pads without insulating material are used, then CuP positioning density can be increased, but manufacturing precision deteriorates due to small tolerances leading to short circuits and alignment issues
Solution Approach 1:
The contact pad is segmented into multiple regions: an intermediate portion exposed above the solder resist layer for CuP bonding, and end portions covered by the solder resist layer. This segmentation allows the CuP to bond to the exposed intermediate portion while the solder resist covers the end portions, preventing shorts between adjacent traces and enabling higher CuP density with relaxed alignment tolerances.
Solution Approach 2:
The solder resist layer acts as an intermediary element between the conductive trace and the external environment. By positioning the solder resist layer to cover the end portions of the trace while leaving the intermediate portion exposed, it mediates between the need for high CuP density and the need for manufacturing precision, preventing shorts while enabling dense packaging.
2Measurement precision
If smaller solder resist openings are used to improve alignment, then alignment precision improves, but manufacturing complexity increases due to costly optimization requirements
Solution Approach 1:
The solder resist layer is applied with different qualities at different locations: it is present at the end portions of traces where short prevention is needed, and absent at the intermediate portions where CuP bonding occurs. This local differentiation allows for larger, easier-to-manufacture openings while maintaining both alignment tolerance and short prevention.
3Ease of manufacture
If larger CuP diameters are used, then ease of manufacture improves, but alignment precision deteriorates due to increased tolerance requirements
Solution Approach 1:
The bonding function is extracted from the entire trace and concentrated at the intermediate portion exposed above the solder resist layer. This allows the CuP to be larger in diameter while maintaining precise bonding at the exposed region, as the solder resist covers the rest of the trace to prevent shorts, effectively decoupling CuP size from alignment precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of the flipchip/substrate assembly by preventing shorts and solder resist undercut, allowing for easier alignment and increased CuP density, reducing manufacturing costs and improving product yield.
Implementation Method 1
The CuP's are bonded by this solder piece to corresponding contact pads on a substrate as by reflow heating
Implementation Method 2
Copper pillars are deposited by an electroplating process on chip pads on the top side of the wafer
Data Source
AI summary
An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.