Copper Pillar Digital Lithography for Co-Planarity Control

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Solution Overview

Problem

The challenge in semiconductor packaging is the uneven deposition of metal ions in vias, leading to pillars with varying heights due to factors like via density, diameter, and depth, which affects electrical connectivity and assembly quality.

Innovation Solution

A system and method using digital lithography to adjust the mask pattern based on metrology data, ensuring uniform deposition rates across the substrate by varying the dimensions of vias and pillars, thereby achieving equivalent pillar heights.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithography processes are used with fixed mask patterns, then manufacturing simplicity is maintained, but pillar height uniformity deteriorates due to uneven metal ion deposition

Engineering Contradiction:
Improvepillar height uniformityVSAvoidlithography process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by varying the via dimensions (width and depth) at different locations across the substrate according to a generated mask pattern. This compensates for non-uniform metal ion deposition rates in different regions, ensuring that pillars throughout the entire substrate achieve uniform heights despite spatial variations in deposition conditions

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameters of the via structure (width, depth, and other geometric parameters) based on location-specific deposition characteristics. By adjusting these parameters according to a generated mask pattern that accounts for non-uniform deposition rates, the system achieves uniform pillar heights across the substrate while managing process complexity through automated pattern generation

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If digital lithography with updated mask patterns is implemented, then deposition uniformity is improved, but manufacturing time increases

Engineering Contradiction:
Improvedeposition uniformityVSAvoidmanufacturing cycle time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-generating optimized mask patterns that account for non-uniform deposition characteristics before production begins. This upfront preparation eliminates the need for iterative adjustments during manufacturing, achieving uniform deposition while minimizing the impact on manufacturing cycle time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating a digital model of the substrate and deposition characteristics, then generating mask patterns based on this model. This virtual prototyping and simulation approach allows optimization of deposition uniformity without requiring multiple physical trial runs, thereby reducing manufacturing time while achieving uniform results

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20260044069A1Copper pillar co-planarity using digital lithography
Publication Date: 2026.02.12 APPLIED MATERIALS INC
  • US20260044069A1 patent drawing
  • US20260044069A1 patent drawing
  • US20260044069A1 patent drawing

AI summary

In one or more embodiments, a method includes conducting a first digital lithography process according to a mask pattern to form first vias having a first dimension over a first area and second vias having a second dimension over a second area of a first substrate, the first dimension and the second dimension are different. The method further includes receiving metrology data of first pillars and second pillars. The first pillars and the second pillars having different heights. A digital lithography device generates an updated mask pattern according to the metrology data. The method further includes conducting a second digital lithography process according to the updated mask pattern to form third vias having a third dimension over the first area and fourth vias having a fourth dimension over the second area of a second substrate, the third dimension and the fourth dimension are different.