Copper Pillar Flip Chip Structure for Fine Pitch Solder Reliability
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Solution Overview
Problem
At finer pitches in semiconductor devices, existing methods for forming solder joints become unreliable, leading to increased joint failure due to thermal mismatch between the semiconductor die and substrate, and the limitations of binary solder alloys in electroplating processes.
Innovation Solution
The formation of copper pillars with solder bumps, where a layer of molding compound is used to encapsulate the pillars, allowing for the deposition of solder balls or additional pillars with solder bumps, enabling the use of diverse solder alloys and reducing thermal stress through stress buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder ball size is reduced to accommodate finer pitch arrays, then array pitch is improved, but solder joint reliability deteriorates due to increased thermal mismatch stress
Solution Approach 1:
The patent implements a nested structure where a copper pillar is embedded within the solder joint, creating a multi-layered configuration. The copper pillar is positioned inside the solder ball, which itself is mounted on the contact pad. This nested arrangement allows the copper pillar to provide mechanical support and thermal stress buffering while the solder ball maintains electrical connectivity, thereby enabling finer pitch arrays without compromising solder joint reliability
Solution Approach 2:
The patent employs composite materials by combining copper pillars with solder balls to form a hybrid joint structure. The copper pillar provides high thermal and electrical conductivity along with mechanical strength, while the solder ball provides ductility and electrical connectivity. This composite structure compensates for thermal expansion mismatch between the silicon die and organic substrate, allowing smaller solder balls to be used at finer pitches without increasing joint failure rates
2Ease of manufacture
If copper pillars are formed using electroplating with binary solder alloys, then manufacturing process is simplified, but solder joint performance deteriorates due to limited alloy options
Solution Approach 1:
The patent segments the solder joint formation process into two distinct stages: first forming the copper pillar through electroplating, then depositing solder material separately. This segmentation allows different materials and processes to be optimized independently - the copper pillar can be formed using simple binary electroplating processes, while the solder can be applied using various techniques (screen printing, electroplating, or ball placement) with diverse alloy compositions including lead-free options like SAC305, SnAgCu, or SnZn alloys
Solution Approach 2:
The patent changes the material parameters of the solder joint by allowing transition from binary solder alloys to multi-component lead-free solder alloys. The copper pillar serves as a base that can accommodate various solder compositions, enabling optimization of solder joint properties such as melting point, ductility, and thermal conductivity based on specific application requirements without complicating the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of solder joints at finer pitches by accommodating thermal expansion differences and allowing for the use of multi-metal solder alloys, reducing rejection rates and improving the structural integrity of semiconductor devices.
Implementation Method 1
Copper is then plated onto the seed layer 112 in the openings 115 to form the copper pillars 106
Implementation Method 2
in a reflow step, the solder balls are heated until they melt and form a solder joint between the contact pads of the die and the landing pads of the substrate
Data Source
AI summary
A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars.