Copper Pillar Electrode Structure for Low-Stress Semiconductor Bonding
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Solution Overview
Problem
Current semiconductor devices face manufacturing complexity and potential reliability issues due to the intricate structure of electrode terminals, which include multiple layers and materials like Cu, Ni, and SnAg, leading to difficulties in bonding and stress concentration during the assembly process.
Innovation Solution
The semiconductor device employs a pillar layer with a disc-shaped first portion and a columnar second portion, integrated with a bonding layer that includes a barrier layer and a solder layer, optimized for easier manufacturing and reduced stress concentration by altering the connection geometry between the pillar layers, thereby simplifying the manufacturing process and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple layers and materials (Cu, Ni, SnAg) are used in electrode terminals, then electrical connectivity and bonding capability are improved, but manufacturing complexity and stress concentration increase
Solution Approach 1:
The patent extracts and eliminates the Cu electrode layer and pad electrode layer from the traditional multi-layer structure, retaining only the essential bonding layer with SnAg alloy. This simplification removes unnecessary complexity while preserving the core bonding functionality, directly resolving the contradiction between reliability and manufacturing complexity.
Solution Approach 2:
Instead of building up multiple layers (Cu→Ni→Pd→SnAg) from the substrate, the patent inverts the approach by directly forming the SnAg bonding layer on the semiconductor substrate without intermediate electrode layers. This inversion simplifies the manufacturing process while maintaining bonding capability.
2Reliability
If intricate multi-layer electrode terminal structure is used, then electrical connectivity is improved, but stress concentration and cracking risk increase
Solution Approach 1:
The patent removes the Cu electrode layer and pad electrode layer that create stress concentration points due to their different thermal expansion coefficients and rigid interfaces. By extracting these problematic layers, the structure maintains electrical connectivity through the SnAg bonding layer while significantly reducing stress concentration and cracking risk.
3Reliability
If traditional electrode terminal structure is used, then electrical connectivity is ensured, but manufacturing difficulty increases
Solution Approach 1:
The patent inverts the traditional manufacturing sequence by directly forming the SnAg bonding layer on the semiconductor substrate without first creating Cu electrode layers or Ni/Pd pad layers. This inverted approach reduces the number of deposition and patterning steps, thereby easing manufacturing difficulty while ensuring electrical connectivity through the direct SnAg-substrate interface.
Solution Approach 2:
The patent merges the functions of multiple separate layers (Cu electrode, Ni pad, Pd pad, SnAg bonding layer) into a single integrated SnAg bonding layer structure. This consolidation simplifies the manufacturing process by reducing the number of distinct fabrication steps while maintaining the essential electrical connectivity function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the manufacturing process and reduces the risk of cracking in the sealing resin, improving the reliability and efficiency of the semiconductor device assembly by alleviating stress concentration and eliminating the need for complex Cu electrode and pad electrode layers.
Implementation Method 1
a bonding layer formed on the Cu columnar body... The bonding layer consists of a nickel layer at a side of the Cu columnar body and a solder layer formed on the nickel layer
Data Source
AI summary
A semiconductor device includes: a semiconductor device main body; and an electrode terminal provided at a side of a main surface of the semiconductor device main body and partially protruding outward from the main surface, wherein the electrode terminal includes: a pillar layer made of copper and electrically connected to a wiring layer disposed within the semiconductor device main body; and a bonding layer formed over a surface of the pillar layer on an opposite side of the pillar layer from the wiring layer, and wherein the pillar layer includes: a disc-shaped first portion; and a columnar second portion formed over a central portion of a surface of the first portion on an opposite side of the first portion from the wiring layer.