Micrometer Copper Pillar Arrays for Fine-Pitch Interconnects
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Solution Overview
Problem
Current fabrication processes for fine-pitch micro bump copper pillar arrays in semiconductor devices face challenges in achieving better interconnection performance due to issues like undercut and limited pitch scalability, which affect the reliability and density of interconnects, especially at smaller pitches.
Innovation Solution
A substrate structure with copper pillar arrays having a cylindrical shape, an oxide or nitride layer, and a solder material layer, where the copper pillars are fabricated using a method involving TiW, Ti, or TiN layers, Cu seed layers, and electroplating, with a focus on reducing undercut and achieving high aspect ratios and uniformity, allowing for pitches as low as 5 μm with improved reliability and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for fine-pitch micro bump copper pillar arrays, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to undercut and limited pitch scalability
Solution Approach 1:
The fabrication process is divided into distinct stages: forming sacrificial structures, selective metal deposition, and controlled removal of sacrificial material. This segmentation allows each step to be optimized independently, achieving precise pitch control down to 5 μm while maintaining process manageability
Solution Approach 2:
Sacrificial structures are formed in advance before the final copper pillar fabrication. These preliminary structures serve as templates that define the precise pitch and geometry of the final micro bumps, enabling accurate pitch scalability to 5 μm before the actual metallization process
2Productivity
If pitch is reduced to increase interconnection density, then productivity is improved, but manufacturing precision deteriorates due to undercut
Solution Approach 1:
Sacrificial structures act as intermediary elements that enable precise pitch definition without directly becoming part of the final interconnect. These intermediaries are removed after serving their templating function, eliminating the undercut issue that plagues conventional direct fabrication approaches at reduced pitches
Solution Approach 2:
The conventional mechanical/chemical etching approach that causes undercut is replaced with a deposition-based approach using sacrificial structures. Metal is deposited conformally on predefined templates rather than being etched from a continuous layer, eliminating lateral etching damage and enabling precise pitch control at 5 μm and below
3Reliability
If aspect ratio is increased to improve stand-off height, then reliability is improved, but manufacturing precision deteriorates due to difficulty in forming high aspect ratio structures
Solution Approach 1:
The sacrificial structures are formed with the exact desired aspect ratio before metal deposition. This preliminary definition of geometry ensures that the final copper pillars inherit precise dimensional control, achieving aspect ratios of 2-3 with high uniformity across the array while maintaining reliability through adequate stand-off height
Solution Approach 2:
The aspect ratio is controlled by adjusting parameters of the sacrificial structure formation process (dimensions, pitch, material properties) rather than attempting to directly form high aspect ratio metal structures. This indirect parameter control achieves uniform aspect ratios of 2-3 with better manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the production of micro bump structures with high aspect ratios and reduced undercut, enhancing interconnection density and reliability, particularly suitable for hybrid IR detectors and other high-density applications, and demonstrating compatibility with standard packaging infrastructures.
Implementation Method 1
The base comprises a first TiW, Ti or TiN layer with a thickness of about 30 nm
Implementation Method 2
The base comprises a first TiW, Ti or TiN layer with a thickness of about 30 nm and a second Cu seed layer with a thickness of about 100 nm
Implementation Method 3
a method involving TiW, Ti, or TiN layers, Cu seed layers, and electroplating
Implementation Method 4
each copper pillar structure has an oxide layer or a nitride layer on its surface
Data Source
AI summary
Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided.