Copper Pillar UBM Structure for Thermal Stress-Resistant Packaging
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Solution Overview
Problem
Semiconductor packaging faces challenges due to stress and cracking caused by differences in thermal expansion coefficients between various layers, leading to reliability issues in solder joints, especially in low dielectric constant dielectric layers and solder jointed areas.
Innovation Solution
The use of bump structures with specific dimensions and materials, such as copper pillars and solder layers, along with under-bump metallization and passivation layers, to form reliable electrical connections between substrates, reducing stress and improving structural integrity by optimizing the relationship between pad width, bump pitch, and layer widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are used to connect die to substrate, then electrical connection is achieved, but stress and cracking occur due to different coefficients of thermal expansion between layers
Solution Approach 1:
The patent introduces an under-bump metallization (UBM) layer as an intermediary between the solder bump and the die pad. This UBM layer serves as a stress buffer that absorbs thermal expansion differences between the solder bump and the underlying die structure, preventing stress transmission that would cause cracking in low-k dielectric layers. The UBM layer effectively mediates the mechanical incompatibility between dissimilar materials in the vertical stack.
Solution Approach 2:
The patent employs a composite structure consisting of multiple materials with different mechanical properties: the solder bump (soft, ductile), the UBM layer (intermediate stiffness), and the die pad (rigid). This composite arrangement creates a gradient of mechanical properties that progressively absorbs and distributes thermal stress, preventing stress concentration at any single interface and thereby reducing cracking.
2Reliability
If fine gold wire is used for interconnection, then electrical connection is achieved, but the structure becomes complex and vulnerable to stress
Solution Approach 1:
The patent extracts and eliminates the fine gold wire bonding structure from the interconnection system. Instead of using wire bonds that extend vertically from the die surface, the invention implements direct solder bump connections that integrate the interconnection function into the die pad itself. This extraction simplifies the packaging structure by removing unnecessary components and reducing the number of stress-prone interfaces.
Solution Approach 2:
The patent merges the electrical connection function with the mechanical support structure by integrating the interconnection directly into the die pad through solder bumps. Rather than having separate wire bonds for electrical connection and mechanical support, the solder bump serves both functions simultaneously, reducing structural complexity and the number of potential failure points.
3Quantity of substance
If pad pitch is reduced to increase integration density, then more components fit in given area, but stress concentration increases leading to more cracking
Solution Approach 1:
The under-bump metallization layer acts as a stress-distributing intermediary that becomes increasingly important as pad pitch decreases. With smaller spacing between pads, stress from thermal expansion cannot dissipate as easily, so the UBM layer provides a localized stress absorption zone at each bump location, preventing stress concentration even when pads are densely packed.
Solution Approach 2:
The patent modifies the mechanical parameters of the interconnection system by changing the material composition and thickness of the UBM layer. By adjusting these parameters, the stress distribution characteristics are optimized to handle high-density configurations, allowing reduced pad pitch without proportionally increasing stress concentration and cracking risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described bump structure design enhances joint reliability, reduces bump fatigue, and minimizes stress and cracking, thereby improving the overall reliability and durability of semiconductor packages.
Implementation Method 1
The different layers making up the interconnection typically have different coefficients of thermal expansion (CTEs). As a result, a relatively large stress derived from this difference is exhibited on the joint area
Implementation Method 2
which often causes cracks to form and propagate to low dielectric constant (low-k) dielectric layers or to the solder jointed area
Data Source
AI summary
A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.