Copper Pillar Redistribution Layer for Fine-Pitch Via Packaging
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Solution Overview
Problem
Existing fan-out wafer-level packaging processes face issues such as poor via morphology and photoresist residues due to production line variations, leading to yield loss and reliability risks, particularly in fine-pitch evolution requiring high via interconnection density.
Innovation Solution
A chip packaging structure with a redistribution layer comprising first and second copper pillar layers and a metal routing layer, where copper pillars are formed using a photoresist with better photosensitivity, allowing for smaller vias and improved coplanarity through chemical mechanical planarization, eliminating the need for photosensitive polyimide and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photosensitive polyimide (PSPI) is used as the dielectric material for via formation, then the via formation process can be completed, but poor via morphology and photoresist residues occur due to production line variations
Solution Approach 1:
The patent extracts the problematic photosensitive polyimide (PSPI) material from the via formation process and replaces it with a two-layer structure: a non-photosensitive polyimide layer for mechanical support and a separate photoresist layer for precise via patterning. This separation eliminates the interaction between photosensitive properties and dielectric function that caused morphology issues, while the photoresist layer alone provides the necessary photosensitivity for accurate via formation without leaving residues.
2Quantity of substance
If the via size and pitch are reduced to increase interconnection density, then fine-pitch evolution is achieved, but the capability of PSPI for vias becomes insufficient
Solution Approach 1:
The patent changes the material parameter of the photoresist layer to have better photosensitivity and resolution characteristics than PSPI. This parameter change enables the formation of smaller vias with tighter pitch by allowing more precise pattern definition during photolithography, directly supporting fine-pitch evolution and increased interconnection density while maintaining manufacturing precision.
3Manufacturing precision
If chemical mechanical planarization (CMP) is applied to copper pillar surfaces, then coplanarity is improved, but process complexity increases
Solution Approach 1:
The patent applies chemical mechanical planarization (CMP) to the copper pillar surfaces after copper deposition but before subsequent packaging steps. This preliminary planarization action ensures that the copper pillars have flat, coplanar top surfaces, which facilitates accurate alignment and bonding in subsequent packaging processes. By performing this planarization early in the process, the patent prevents accumulation of surface irregularities that would complicate later steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution supports the evolution of smaller vias, enhances interconnection density, and improves reliability by ensuring coplanarity and reducing warpage, thus addressing yield loss and reliability issues in fan-out packaging.
Implementation Method 1
the applied PSPI is subjected to photoetching and development to form vias (via)
Implementation Method 2
The first copper pillars and the second copper pillars that are of upright pillar structures are formed based on good photosensitivity of the photoresist
Implementation Method 3
surfaces of the first copper pillar layer and the second copper pillar layer can be separately ground through chemical mechanical planarization (chemical mechanical planarization, CMP) to form flat interfaces
Implementation Method 4
followed by electroplating with copper to form an RDL
Data Source
Figure 1~2
Figure 3~4(b)
Figure 5
AI summary
This application provides a chip packaging structure and a preparation method thereof, and an electronic device, and relates to the field of chip technologies. A redistribution layer used in the chip packaging structure can support subsequent evolution for smaller vias. The chip packaging structure includes a redistribution layer, and the redistribution layer includes a first copper pillar layer, a second copper pillar layer, and a metal routing layer. The first copper pillar layer includes a plurality of first copper pillars, and the second copper pillar layer includes a plurality of second copper pillars. The metal routing layer is located between the first copper pillar layer and the second copper pillar layer, and the metal routing layer is electrically connected to the plurality of first copper pillars and the plurality of second copper pillars. The plurality of first copper pillars and the plurality of second copper pillars are of upright pillar structures. The plurality of first copper pillars are coplanar on a side close to the metal routing layer, and the plurality of second copper pillars are coplanar on a side away from the metal routing layer.