Copper Plated Segments for Multi-Die Stack Interconnection
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Solution Overview
Problem
Current semiconductor packaging technologies, such as wire bonding and flip-chip, face challenges with high manufacturing costs, performance degradation due to parasitic inductance and capacitance, long die interconnections leading to signal latency, and reliability issues like wire bonding shorting.
Innovation Solution
A multi-die package is constructed using a base substrate with copper plated segments for die interconnection, where each die is integrated with the substrate in the same layer using copper plating, reducing connection lengths and eliminating the need for expensive gold wires and complex ball attachment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding or flip-chip technology is used for interconnection, then manufacturing process is established, but manufacturing costs increase and throughput decreases
Solution Approach 1:
The patent combines substrate manufacturing and assembly manufacturing into a single integrated process. Multiple dice are stacked and interconnected within the same package during substrate fabrication, eliminating separate wire bonding or flip-chip assembly steps. This merging of processes reduces manufacturing complexity and improves throughput by performing interconnections inline with substrate production.
2Reliability
If wire bonding or flip-chip technology is used for interconnection, then connection is established, but package parasitic inductance, resistance, and capacitance increase leading to performance degradation
Solution Approach 1:
The patent implements localized copper plated segments directly on the substrate at each die location. This local interconnection approach creates short, direct conductive paths between stacked dice, minimizing the length of interconnect traces. The localized quality of copper plating at specific die positions reduces parasitic inductance, resistance, and capacitance compared to extended wire bonding or flip-chip bump connections.
3Reliability
If traditional interconnection methods are used, then die connection is established, but die interconnections are long causing high signal latency and reducing operating frequency
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical stacking. Multiple dice are positioned one on top of another in the vertical dimension, with copper plated segments providing direct vertical interconnections. This dimensional change from 2D to 3D architecture dramatically shortens interconnection paths, reducing signal latency and enabling higher operating frequencies while maintaining reliable die-to-die connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in faster electrical response times, reduced manufacturing costs, smaller package size, and increased reliability by integrating multiple dice in a single package with shorter interconnects and eliminating wire bonding issues.
Implementation Method 1
copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.
Data Source
AI summary
An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.