Void-Free Copper Fill via Plating and Annealing
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Solution Overview
Problem
Current semiconductor processing technologies face challenges in filling small, high aspect ratio features with copper due to void formation and the need for a copper seed layer deposited via physical vapor deposition, which limits feature sizes below 18 nanometers.
Innovation Solution
A method involving sequential plating and annealing of copper layers on a wafer substrate with a liner layer, where the copper layer is redistributed from field regions to features through annealing in a reducing atmosphere, eliminating the need for a copper seed layer and enabling void-free filling of features down to 100 nanometers in size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical vapor deposition is used to deposit copper seed layer, then copper can be deposited on barrier layer, but feature sizes are limited below 18 nanometers due to void formation
Solution Approach 1:
The copper deposition process is divided into multiple sequential electroplating steps rather than a single step. Each step deposits a portion of the required copper thickness, allowing better control over filling small high aspect ratio features and preventing void formation while achieving the desired feature sizes below 18 nanometers
Solution Approach 2:
The electroplating process is performed in periodic cycles with intermediate annealing steps. Each cycle consists of electroplating followed by annealing, which redistributes copper and promotes void-free filling. This periodic repetition of plating and annealing enables precise control over copper distribution in sub-18nm features
2Productivity
If electroplating is used to fill trenches and vias, then copper can be deposited onto conductive layer, but copper seed layer is required first which increases process complexity
Solution Approach 1:
The copper seed layer deposition step is completely removed from the process flow. Instead of depositing a separate copper seed layer via PVD or CVD, the invention directly performs electroplating onto the barrier layer, eliminating the need for intermediate seed layer formation and reducing overall process complexity
Solution Approach 2:
The barrier layer itself serves as the substrate for direct electroplating without requiring a separate copper seed layer. The electroplating process is adapted to initiate copper deposition directly on the barrier layer, making the system self-sufficient and eliminating an entire process module
3Reliability
If multiple plating cycles are performed, then void-free filling can be achieved, but processing time increases
Solution Approach 1:
The annealing temperature and duration are optimized to achieve effective copper redistribution in minimal time. By carefully controlling these thermal parameters, the process achieves void-free filling in fewer cycles, reducing total processing time while maintaining high reliability
Solution Approach 2:
The electroplating and annealing cycles are designed to continuously progress the copper filling toward completion without idle steps. Each cycle builds upon the previous one with no gaps, maintaining continuous useful action that efficiently achieves void-free filling while minimizing total processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient, void-free filling of small features with copper, maintaining the liner layer in a reduced state and reducing the complexity of the semiconductor processing by eliminating the requirement for a copper seed layer, thereby improving the aspect ratio and feature filling capabilities.
Implementation Method 1
A copper layer is plated onto the surface of the wafer substrate with an electroplating process
Implementation Method 2
The copper layer is then annealed, with the annealing redistributing copper from regions of the wafer substrate to the feature
Implementation Method 3
the annealing redistributing copper from regions of the wafer substrate to the feature
Implementation Method 4
The liner layer may be annealed in a reducing atmosphere prior to plating the copper layer
Data Source
AI summary
Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.