Copper Plating Film with Impurity Gradient for Void Reduction
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Solution Overview
Problem
The formation of micro-voids during the creation of copper wiring in semiconductor devices leads to reduced electromigration (EM) and stress migration (SM) reliability, as existing methods like bias sputter copper diffusion do not effectively inhibit crystal grain growth and void formation.
Innovation Solution
A method involving the formation of a plating film with a higher impurity concentration in the upper portion than the lower portion, achieved by controlling current density, applied voltage, or rotational frequency during electrolytic plating, followed by thermal treatment and chemical mechanical polishing to bury the film in recessed portions, thereby controlling crystal grain growth and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electrolytic plating is used to form Cu film with additives, then burying property and flatness are improved, but micro-voids occur and reliability is degraded
Solution Approach 1:
The patent applies local quality by creating a Cu film with non-uniform impurity distribution, where the upper portion has higher impurity concentration than the lower portion. This gradient structure allows the upper surface to maintain good flatness and burying properties while the lower portion remains relatively pure to prevent micro-void formation during thermal treatment, thus resolving the contradiction between manufacturing precision and reliability.
2Reliability
If bias sputter copper is diffused into plated copper film, then EM and SM reliability are enhanced, but crystal grain growth causes void growth during thermal treatment
Solution Approach 1:
The patent applies preliminary action by pre-distributing impurities during the electrolytic plating process before thermal treatment occurs. The impurity gradient is established in advance so that when thermal treatment and crystal grain growth occur later, the impurities are already positioned to suppress void formation rather than allowing voids to grow during the thermal process.
3Productivity
If current density is increased during plating, then productivity is improved, but impurity distribution becomes non-uniform and micro-voids occur
Solution Approach 1:
The patent applies dynamics by dynamically adjusting the current density during the plating process. The current density is changed over time to achieve a specific impurity distribution profile, allowing the process to maintain high productivity while intentionally creating the desired non-uniform impurity distribution that prevents micro-void formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of copper wiring by reducing micro-voids and crystal defects, improving the overall reliability of semiconductor devices against EM and SM by ensuring uniform impurity distribution and controlled crystal growth.
Implementation Method 1
different kinds of elements diffuse in the plated copper film by thermal treatment
Implementation Method 2
thermally treating the plating film
Implementation Method 3
electrolytic plating is widely used
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.