Copper Plating Chamber Control for Void-Free Narrow Gap Filling
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Solution Overview
Problem
The challenge of filling narrower gaps in copper interconnection structures with electroplating becomes difficult due to high resistivity of thinner Cu seed layers and new seed layer materials, leading to voids and plating failures in semiconductor devices as current technologies rely on direct current mode plating.
Innovation Solution
A plating method and apparatus that utilizes a divided anode chamber with independent zones and power supply control, combined with a segmented cathode chamber and controlled plating solution distribution, to achieve precise and efficient copper deposition in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct current mode plating is used to fill narrower gaps, then plating rate can be maintained, but voids form and plating fails due to high resistivity of thinner seed layers
Solution Approach 1:
The patent applies periodic pulsed direct current plating instead of continuous direct current. The plating process uses alternating on-off cycles where current is applied in pulses with specific duty cycles. During the on-phase, copper ions are reduced and deposited on the substrate. During the off-phase, diffusion and mass transport replenish copper ions in the gap regions. This periodic action prevents void formation while maintaining adequate plating rate by allowing ion redistribution during the off-period, resolving the contradiction between productivity and plating quality.
Solution Approach 2:
The patent dynamically adjusts plating parameters including current density, pulse width, and duty cycle during the plating process. The system transitions from static direct current to dynamic pulsed current with variable parameters. By optimizing the pulse characteristics and adjusting current density dynamically, the process accommodates varying gap widths and seed layer resistivities, maintaining both plating rate and preventing defects, thus resolving the contradiction between productivity and reliability.
2Productivity
If increasing plating current is applied to raise plating rate, then deposition speed increases, but voids form in small gaps
Solution Approach 1:
The patent employs pulsed direct current with optimized pulse width and duty cycle to enable high deposition speed without void formation. During the pulse on-time, high current density drives rapid copper deposition. During the pulse off-time, copper ions diffuse into the gap regions replenishing the depleted ion concentration. This periodic modulation allows the system to achieve high average deposition rates while preventing the ion depletion that causes voids, thus resolving the contradiction between productivity and manufacturing precision.
Solution Approach 2:
The patent changes the electrical parameter from continuous direct current to pulsed direct current with variable current density, pulse width, and duty cycle. By optimizing these parameters, the system achieves high deposition rates during the on-phase while allowing ion replenishment during the off-phase. This parameter optimization enables simultaneous achievement of high productivity and precise gap filling without voids, resolving the contradiction between deposition speed and gap filling quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform copper layer deposition, minimizing voids and improving the reliability of interconnection structures by optimizing power supply and electrolyte distribution, thereby enhancing the manufacturing process for semiconductor devices.
Implementation Method 1
depositing Cu layer on the seed layer and filling the recessed areas with Cu... electroplating has excellent gap filling capability and higher deposition rate
Data Source
AI summary
The present invention discloses a plating apparatus and plating methods for plating metal layers on a substrate. In an embodiment, a plating method comprises: step 1: immersing a substrate into plating solution of a plating chamber assembly including at least a first anode and a second anode; step 2: turning on a first plating power supply applied on the first anode, setting the first plating power supply to output a power value P11 and continue with a period T11; step 3: when the period T11 ends, adjusting the first plating power supply applied on the first anode to output a power value P12 and continue with a period T12, at the same time, turning on a second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P21 and continue with a period T21; and step 4: when the period T21 ends, adjusting the second plating power supply applied on the second anode to output a power value P22 and continue with a period T22; wherein step 2 to step 4 are performed periodically.