Copper Plug SRAM Cell Area Reduction
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Solution Overview
Problem
Current SRAM technologies face challenges in reducing memory cell size due to increased contact resistance and complex lithography processes, and the use of tungsten plugs results in high resistance values that hinder transistor performance as gate lengths shrink.
Innovation Solution
The implementation of copper-containing plugs and interconnections with specific geometries and processing methods, such as single and dual damascene techniques, to reduce contact resistance and maintain low plug resistance, allowing for smaller transistor sizes and simplified lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If tungsten plugs are used in conventional SRAM structures, then the manufacturing process is simplified, but the plug resistance becomes excessively high which deteriorates transistor performance
Solution Approach 1:
The patent changes the material parameter from tungsten to copper, which has fundamentally different electrical properties. Copper provides lower resistivity (improving plug resistance) while still being compatible with standard semiconductor manufacturing processes, thus resolving the contradiction between ease of manufacture and reliability
Solution Approach 2:
The patent employs a composite structure with copper plugs embedded in a barrier metal layer (such as tantalum or tungsten nitride) which is then integrated into the insulating film. This composite approach maintains manufacturing compatibility through the barrier layer while achieving low resistance through the copper core
2Area of stationary object
If memory cell size is reduced to downsize electronic devices, then device integration increases, but contact resistance increases which deteriorates transistor performance
Solution Approach 1:
By changing the plug material from tungsten to copper, the electrical conductivity parameter is improved, which compensates for the increased contact resistance that occurs when memory cell dimensions are reduced. This allows continued scaling while maintaining performance
Solution Approach 2:
The patent extends the plug structure vertically by forming it to penetrate through multiple insulating film layers. This vertical dimensionality increase provides a larger contact area and shorter current path, compensating for the reduced horizontal dimensions of scaled-down memory cells
3Speed
If gate length is shortened to improve transistor speed, then operation frequency increases, but plug resistance increases which counteracts the performance gain
Solution Approach 1:
The material change to copper fundamentally improves the electrical conductivity parameter, ensuring that even as gate lengths are shortened and feature sizes are reduced, the plug resistance remains low enough to support high-speed operation without becoming the limiting factor
4Reliability
If copper plugs are used to reduce resistance, then plug conductivity improves, but manufacturing complexity increases due to additional processing steps
Solution Approach 1:
The patent merges the copper plug formation process with the existing insulating film formation and patterning processes. The copper is deposited and patterned as part of the same fabrication sequence used for creating the insulating structures, thereby integrating a new material system into an existing manufacturing flow without proportionally increasing complexity
Data Source
AI summary
A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.