Copper-on-Polyimide RDL Patterning for Denser Semiconductor Wiring
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Solution Overview
Problem
Redistribution layers (RDLs) in semiconductor devices add additional layers, increasing fabrication time, size, resistivity, and failure risks due to dielectric films and multiple layers of lines and vias.
Innovation Solution
Utilizing polyimide planarization and dual-level metallization with resist patterning to form RDLs, reducing the need for direct polyimide patterning and improving control over geometries, thereby enhancing electrical characteristics and wiring density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional RDL fabrication with multiple dielectric layers and direct polyimide patterning is used, then connections can be established between different chip parts, but fabrication time increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates unnecessary intermediate dielectric layers from the traditional RDL structure. By using direct copper-on-polyimide metallization without intermediate dielectric films, the invention reduces the total number of layers while maintaining the essential function of electrical redistribution, thereby reducing fabrication time and manufacturing complexity
Solution Approach 2:
The patent applies preliminary planarization to the polyimide layer before metallization to ensure a flat surface for copper deposition. This preliminary preparation enables direct copper patterning on polyimide without requiring subsequent dielectric layer additions, reducing overall fabrication steps and time
2Adaptability or versatility
If additional dielectric layers and multiple lines/vias are added to achieve desired connections, then routing flexibility is improved, but manufacturing precision requirements increase and failure risks increase
Solution Approach 1:
The patent changes the material parameter by using copper directly on polyimide instead of traditional copper-on-dielectric structures. This material parameter change enables better geometric control and manufacturing precision because copper forms adherent patterns directly on the planarized polyimide surface, reducing alignment errors and dimensional variations while maintaining routing flexibility
Solution Approach 2:
The patent creates a composite structure of copper metallization directly bonded to polyimide substrate. This composite material approach provides both mechanical stability and electrical conductivity in a single integrated layer, reducing the need for multiple separate layers and improving geometric control while maintaining design flexibility
3Adaptability or versatility
If multiple layers of lines and vias are used to achieve redistribution, then connection routing is improved, but resistivity increases and reliability decreases
Solution Approach 1:
The patent merges the functions of multiple separate dielectric and metal layers into a single integrated copper-on-polyimide structure. By combining what would traditionally require multiple sequential layers into one direct metallization layer, the invention reduces the total number of interfaces and potential failure points, thereby improving reliability and reducing resistivity while maintaining connection routing capabilities
Data Source
AI summary
A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.