Copper Post Bump Cup Geometry for Solder Bridging Prevention

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Solution Overview

Problem

The challenges in chip packaging include solder bridging, flux residue, and underfill voids due to reduced bump pitch and width, leading to signal errors, shorting, and early bump failure, which are exacerbated by the difficulty in flux removal and the formation of inter-metallic compounds between copper and solder.

Innovation Solution

The use of copper post bumps with specific dimensions and a process flow involving flux application and controlled solder reflow, followed by careful flux removal and underfill formation, to maintain an optimal standoff and α ratio, preventing solder bridging and ensuring complete flux removal and void-free underfills.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bump pitch and width are reduced to increase circuit density, then productivity and integration are improved, but solder bridging and shorting risks increase

Engineering Contradiction:
Improvecircuit densityVSAvoidsolder bridging risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the geometric parameters of the bump structure by introducing a cup-shaped configuration with specific depth-to-diameter ratios. This parameter modification allows reduced bump pitch and width while maintaining adequate solder flow control, preventing bridging even at higher densities

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The cup-shaped bump structure utilizes curvature in its geometry, with the凹陷 (depression) forming a concave surface that naturally directs solder flow. This curved geometry prevents solder from spreading laterally between adjacent bumps, reducing bridging risk while allowing closer bump spacing

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If flux is used to facilitate solder reflow, then bonding reliability is improved, but flux residue and cleaning difficulty increase

Engineering Contradiction:
Improvebonding reliabilityVSAvoidflux residue
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The cup-shaped bump structure extracts or contains the flux within its凹陷 (depression) during the soldering process. The geometry naturally traps flux in the cup interior, preventing it from spreading across the surface and leaving residue on surrounding areas, thereby reducing cleaning requirements

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If copper posts are used to form bumps, then electrical conductivity is improved, but inter-metallic compound formation with solder increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidinter-metallic compound formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent employs a composite material structure with the cup-shaped bump consisting of copper post combined with other materials. This composite approach maintains the electrical conductivity benefits of copper while the additional material layers control or reduce unwanted inter-metallic compound formation with the solder

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the risk of solder shorting and flux residue, enhancing the reliability and yield of chip packages by maintaining an optimal standoff and α ratio, thus preventing early bump failure and ensuring proper underfill protection.

Implementation Method 1

solder reflowing

Methodology Applied
Scientific EffectSolder reflow: Melting

Data Source

PatentUS9711475B2Bump structural designs to minimize package defects
Publication Date: 2017.07.18 PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
  • US9711475B2 patent drawing
  • US9711475B2 patent drawing
  • US9711475B2 patent drawing

AI summary

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.