Front Side Copper Post Joint Structure for TSV Applications
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density and interconnection complexity in two-dimensional integrated circuits, leading to increased circuit RC delay and power consumption, which are addressed by adopting three-dimensional integrated circuits and through-substrate vias, but these solutions require improved interconnect structures for efficient connectivity and protection during manufacturing.
Innovation Solution
A novel interconnect structure is developed using copper posts and a specific manufacturing process involving a via-first or via-last approach, with copper posts formed over semiconductor substrates, and a combination of conductive barrier layers and solder, allowing for controlled thickness and pitch, and enhanced protection during backside grinding and bonding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-substrate vias are used to connect dies in 3D ICs, then interconnection density is improved, but manufacturing complexity and risk of damage during processing increase
Solution Approach 1:
The patent applies preliminary action by forming copper posts and protective structures on the front side of the substrate before performing backside grinding and bonding operations. This ensures that interconnect structures are established and protected in advance, preventing damage during subsequent manufacturing steps and reducing overall manufacturing complexity.
Solution Approach 2:
The patent implements beforehand cushioning by creating protective structures including copper posts, barrier layers, and fill materials that cushion and protect the TSV interconnect structures during backside grinding and bonding. These protective elements prevent mechanical damage to the vias and interconnects during processing, reducing manufacturing complexity and yield losses.
2Ease of manufacture
If backside grinding and bonding are performed without protective structures, then manufacturing simplicity is maintained, but internal structures risk damage
Solution Approach 1:
The patent implements beforehand cushioning by creating protective structures including copper posts, barrier layers, and fill materials that cushion and protect the TSV interconnect structures during backside grinding and bonding. These protective elements prevent mechanical damage to the vias and interconnects during processing, reducing manufacturing complexity and yield losses.
Solution Approach 2:
The patent uses intermediary protective structures such as copper posts, barrier layers, and fill materials that act as mediators between the fragile internal TSV interconnects and the mechanical processing operations. These intermediaries absorb mechanical stresses and protect the internal structures during backside grinding and bonding while maintaining manufacturing feasibility.
3Ease of manufacture
If copper post thickness is not controlled precisely, then manufacturing ease is improved, but shorting risk increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling copper post thickness through electroplating parameters, barrier layer thickness, and etch selectivity ratios. By optimizing these parameters, the patent achieves precise thickness control that prevents shorting while maintaining ease of manufacture through standardized processing conditions and tolerance specifications.
Solution Approach 2:
The patent replaces mechanical tolerance control with electrochemical precision by using electroplating to deposit copper posts with controlled thickness. This substitution of mechanical dimensional control with electrochemical deposition allows precise thickness control at the micrometer and sub-micrometer scale, preventing shorting while maintaining manufacturing ease through process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables better control over copper post thickness and pitch, reducing the risk of shorting and improving the protection of internal structures, while allowing for more efficient and dense interconnects in three-dimensional integrated circuits.
Implementation Method 1
a copper post is formed using an electroplating process
Implementation Method 2
a conductive barrier layer is formed over the copper post
Data Source
AI summary
A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A dielectric buffer layer is formed over at least a portion of the conductive pad, and an under-bump-metallurgy (UBM) is formed directly coupled to the conductive pad, wherein the UBM extends over at least a portion of the dielectric buffer layer. Thereafter, a conductive pillar is formed over the UBM, and one or more conductive materials are formed over the conductive pillar. The substrate may be attached to a carrier substrate using an adhesive.