3D Copper Re-Wiring Layout for Low-Resistance Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the resistance of copper re-wirings as they are expected to carry larger electric currents, necessitating further improvements in conductivity.
Innovation Solution
The semiconductor device incorporates a re-wiring structure with a first re-wiring and a second re-wiring, where the second re-wiring has a greater dimension than the first, allowing for reduced resistance by using a larger copper conductive layer, and is applied only where necessary to maintain a fine wiring layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the Cu re-wiring is increased to reduce resistance, then the resistance decreases and current carrying capacity improves, but the wiring layout becomes coarser and device size increases
Solution Approach 1:
The patent transitions from planar re-wiring to three-dimensional vertical re-wiring. The Cu re-wiring extends in the thickness direction (vertical dimension) rather than only in the plane, allowing current to flow through a larger cross-sectional area without increasing the device footprint. This dimensional change resolves the contradiction by enabling low resistance while maintaining fine wiring layout.
Solution Approach 2:
The Cu re-wiring is embedded within the resin mold material in a nested configuration. The re-wiring is surrounded and protected by the resin, allowing the conductive path to be integrated within the package structure rather than occupying additional external space. This nesting enables reduced resistance without coarser wiring layout.
2Reliability
If the area of the Cu re-wiring is increased to reduce resistance, then the resistance decreases and current carrying capacity improves, but the device size increases
Solution Approach 1:
The patent utilizes the thickness direction (vertical dimension) to increase the effective cross-sectional area of the Cu re-wiring. By extending the re-wiring vertically within the resin mold rather than expanding horizontally, the device achieves lower resistance without increasing its planar footprint, thus resolving the contradiction between resistance reduction and device size control.
3Reliability
If a larger Cu re-wiring is used to carry large electric currents, then the current carrying capacity improves, but the wiring layout becomes less fine
Solution Approach 1:
The patent achieves high current carrying capacity by extending the Cu re-wiring in the vertical thickness direction rather than increasing its planar dimensions. This vertical extension provides a larger effective cross-sectional area for current flow while maintaining fine pitch in the horizontal plane, thus preserving manufacturing precision and fine wiring layout capability.
Data Source
AI summary
A semiconductor device includes a semiconductor element, an electrode located on a first side in a thickness direction of the semiconductor element, a re-wiring located on the first side in the thickness direction with respect to the electrode and electrically connected to the electrode, and a terminal located on the first side in the thickness direction with respect to the re-wiring and electrically connected to the re-wiring. The re-wiring includes a first re-wiring and a second re-wiring. The dimension of the second re-wiring in the thickness direction is greater than the dimension of the first re-wiring in the thickness direction.