Copper Redistribution Layer Planarization for Bonding Reliability
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Solution Overview
Problem
Conductive structures in semiconductor devices, particularly those formed using aluminum copper (AlCu) or copper (Cu) materials, suffer from stress concentrations leading to cracks and bonding defects due to abruptly angled footers or variations in etching profiles, which degrade the quality and reliability of the semiconductor device.
Innovation Solution
Forming conductive structures using a copper material and employing a chemical/mechanical polishing (CMP) process to planarize these structures, resulting in rounded footers and reduced stress concentrations, thereby improving the quality and reliability by enhancing the planarity of the surfaces that join with interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If aluminum copper (AlCu) material is used for conductive structures, then electrical conductivity is improved, but stress concentrations occur leading to cracks and bonding defects
Solution Approach 1:
The patent applies local quality by creating a footer region with different material composition or structure than the main conductive body. This footer region is specifically designed to have enhanced mechanical properties and stress distribution characteristics, while the upper portion maintains optimal electrical conductivity. The footer acts as a localized stress-relief zone that prevents crack propagation without compromising the overall electrical performance of the conductive structure.
Solution Approach 2:
The patent introduces asymmetry by designing the conductive structure with a non-uniform cross-sectional profile, specifically creating an expanded footer region at the base that tapers into the main conductive body. This asymmetric geometry allows the footer to bear and distribute mechanical stresses over a larger area, while the narrower upper portion maintains precise electrical connections. The asymmetric design decouples the mechanical support function from the electrical conduction function.
2Reliability
If copper (Cu) material is used for conductive structures, then electrical conductivity is improved, but variations in etching profiles cause rounded surfaces leading to bonding defects
Solution Approach 1:
The patent applies preliminary action by forming the footer region before the main conductive body during the deposition process. This sequential formation allows the footer to serve as a pre-prepared foundation that defines the boundary conditions for subsequent etching operations. By establishing the footer geometry first, the patent pre-compensates for etching profile variations that would otherwise cause rounding, ensuring that the interface between the conductive structure and interconnect remains planar and suitable for bonding.
Solution Approach 2:
The patent strategically applies curvature by designing the footer region with rounded contours that naturally distribute stress, while maintaining planar bonding surfaces at the interface with interconnect structures. The curved footer geometry provides mechanical compliance and stress relief, whereas the upper bonding surfaces are kept flat through controlled deposition and etching processes, thus achieving both stress reduction and bonding precision.
3Ease of manufacture
If abruptly angled footers are formed in conductive structures, then manufacturing is simplified, but stress concentrations increase causing cracks
Solution Approach 1:
The patent applies spheroidality by replacing the abruptly angled footer geometry with smoothly curved transitions. The footer region features rounded corners and gradual slope changes that eliminate stress concentration points. This curved geometry can be achieved through standard deposition and etching processes using appropriately designed masks, thus maintaining manufacturing simplicity while dramatically improving crack resistance and overall structural reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMP process reduces stress concentrations and rounding of surfaces, leading to improved bonding quality and reliability of semiconductor devices, thereby reducing resource consumption in semiconductor manufacturing.
Implementation Method 1
employing a chemical/mechanical polishing (CMP) process to planarize these structures
Data Source
AI summary
Some implementations described herein provide a semiconductor device including conductive structures formed as part of a copper redistribution layer. Forming the conductive structures includes forming the conductive structures in a masking structure and performing a chemical/mechanical polishing process to planarize the conductive structures. Forming the conductive structures in the masking structure enables the conductive structures to have rounded footers and reduce stress concentrations within the semiconductor device relative to another semiconductor device using an aluminum copper redistribution layer. Additionally, planarizing the conductive structures reduces a rounding of surfaces of the conductive structures that join with interconnect structures to reduce a likelihood of bonding defects.