Copper Seed Layer Formation via Self-Assembled Monolayer
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Solution Overview
Problem
In the formation of copper lines for ULSI semiconductor devices, existing methods using electroless plating often result in unwanted voids and seams due to the wide size distribution of catalytic particles, compromising the reliability of the copper lines as line widths decrease to the nanometer level.
Innovation Solution
A method involving the formation of a self-assembled monolayer on the semiconductor substrate, with catalytic particles adsorbed at uniform intervals, allows for the deposition of a copper seed layer using electroless plating, ensuring a uniform thickness and minimizing voids and seams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sensitizing-activation method with wide size distribution catalytic particles is used, then copper seed layer can be formed, but unwanted agglomeration of catalytic particles occurs creating voids and seams
Solution Approach 1:
The patent changes the size parameter of catalytic particles from a wide distribution (several nanometers to several micrometers) to a uniform nanometer scale (5-50 nm). This parameter change prevents agglomeration and ensures uniform copper seed layer formation, directly resolving the contradiction between reliability and manufacturing precision.
Solution Approach 2:
The patent introduces a self-assembled monolayer (SAM) as an intermediary between the substrate and catalytic particles. The SAM provides uniform anchoring sites for nanometer-scale catalytic particles, preventing their agglomeration and ensuring uniform distribution. This intermediary enables precise control of particle placement, resolving the uniformity issue while maintaining reliability.
2Productivity
If line widths decrease to nanometer level, then higher integration is achieved, but resistance increases and EM/SIM characteristics deteriorate
Solution Approach 1:
The patent changes the material parameter from aluminum to copper, which has lower resistance (1.7 μΩcm vs 2.65 μΩcm) and superior EM/SIM characteristics. This material parameter change enables nanometer-scale line widths to maintain good electrical characteristics, resolving the contradiction between integration density and reliability.
3Manufacturing precision
If electroless plating is used to fill copper layer, then voids and seams are reduced, but uniform copper seed layer formation at ULSI scale is challenging
Solution Approach 1:
The patent changes the scale parameter to nanometer-level precision (5-50 nm particle size) and combines it with self-assembled monolayer formation. This enables uniform copper seed layer formation at ULSI scale through electroless plating, making the process both precise and manufacturable.
Solution Approach 2:
The patent employs self-assembly processes where the monolayer automatically forms uniform structures and catalytic particles self-organize on the monolayer surface. This self-service mechanism simplifies the manufacturing process while achieving nanometer-scale uniformity, resolving the ease of manufacture challenge.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of copper lines by preventing voids and seams, enabling the successful formation of copper lines with improved electrical characteristics and reliability at the ULSI scale.
Implementation Method 1
catalytic particles adsorbed at uniform intervals
Implementation Method 2
In electroless plating, a metal layer is formed through self-oxidation and reduction without supplying electrons from an outside source
Data Source
AI summary
A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.