Copper-Titanium Double Layer Wiring for TFT Array Panels
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Solution Overview
Problem
As the size of thin film transistor array panels increases, RC delay due to resistance and capacitance in wiring becomes a significant issue, and using copper wiring, while reducing delay, is difficult to etch and contact with other layers, and prone to oxidation and corrosion.
Innovation Solution
A thin film transistor array panel is designed with a double layer of copper and titanium wiring, where the copper and titanium layers are separately etched to form a fine pattern, using a nonperoxide-based etchant to reduce resistance and improve stability, and a gate insulating layer with varying thicknesses to enhance the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper wiring is used to reduce resistance and RC delay, then electrical conductivity improves, but etching difficulty and oxidation resistance worsen
Solution Approach 1:
The patent employs a composite wiring structure consisting of a copper layer and a titanium layer. The copper layer provides low resistance and high electrical conductivity, while the titanium layer offers excellent etchability and oxidation resistance. This composite material approach allows the wiring to simultaneously achieve low RC delay through the copper's electrical properties and manufacturability through the titanium's etching characteristics, directly resolving the technical contradiction between conductivity and ease of manufacture.
2Ease of manufacture
If a double layer of copper and titanium is used, then etching stability improves, but device complexity increases
Solution Approach 1:
The wiring is segmented into two distinct functional layers: a copper layer optimized for electrical conductivity and a titanium layer optimized for etching performance and oxidation resistance. This segmentation allows each layer to be independently optimized for its specific function, with the copper providing low resistance and the titanium providing etch stability and protective properties, thereby achieving high etching stability while managing complexity through functional division.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces RC delay, improves etching and contact stability, and prevents oxidation and corrosion, resulting in a more efficient and reliable thin film transistor array panel.
Implementation Method 1
A nonperoxide-based etchant may be used when the layer that includes copper and the layer that includes titanium are etched
Data Source
AI summary
A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.