Copper TSV Annular Air Gap Isolation for Chip Thermal Stress
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Solution Overview
Problem
The thermal expansion mismatch between copper TSV structures and silicon wafers in three-dimensional chip packaging leads to thermal stress, delamination, and electrical failures, affecting the qualification rate of chips.
Innovation Solution
A chip design incorporating a TSV hole with a shallow trench isolation and an air gap in the isolation material to reduce thermal stress on electrical elements, using a multi-stage isolation structure with air gaps to buffer thermal expansion, thereby improving the chip's qualification rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If copper TSV structures are used for vertical conduction in three-dimensional packaging, then interconnection distance is shortened and operation efficiency is improved, but thermal expansion mismatch with silicon wafers causes thermal stress and delamination
Solution Approach 1:
An air gap is introduced as an intermediary layer between the copper TSV structure and the silicon wafer. This air gap acts as a stress buffer that absorbs thermal expansion mismatch between copper and silicon, preventing direct stress transmission to electrical elements while maintaining the vertical conduction function of the TSV structure.
Solution Approach 2:
The air gap is pre-formed in the isolation material surrounding the TSV hole before final chip assembly. This beforehand cushioning structure is designed to anticipate and absorb thermal stress during subsequent thermal cycling, protecting electrical elements from stress-induced failures before they occur.
2Productivity
If TSV technology is applied to reduce interconnection delay, then bandwidth and storage capacity are improved, but thermal stress from thermal expansion affects electrical elements
Solution Approach 1:
The air gap serves as a mediator between the high-bandwidth TSV structure and the vulnerable electrical elements. It transmits minimal stress while allowing the TSV structure to maintain its full bandwidth capability for high-speed data transmission between stacked chips.
Solution Approach 2:
The isolation material surrounding the TSV hole is modified by introducing an air gap specifically in the region where thermal stress concentrates. This local modification preserves the overall TSV structure's high-bandwidth function while protecting specific vulnerable areas from thermal stress.
3Reliability
If copper is used as conductive material in TSV holes, then vertical conduction between stacked chips is realized, but coefficient of thermal expansion mismatch causes delamination
Solution Approach 1:
The air gap in the isolation material acts as a mediator that decouples the thermal expansion behavior of copper from the silicon substrate. This allows the copper TSV to maintain its excellent electrical conduction properties while the air gap absorbs dimensional changes, preventing delamination and preserving structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap in the isolation material effectively reduces the influence of thermal expansion on electrical elements, minimizing failures and enhancing the chip's qualification rate by alleviating thermal stress and maintaining the integrity of silicon lattices.
Implementation Method 1
The Coefficient of Thermal Expansion (CTE) of copper is 17.8×10 -6, which is larger than that of silicon (2.6×10 -6). Therefore, when a TSV hole is formed on a silicon wafer and copper is filled in the TSV hole, thermal expansion of the copper TSV hole structure affects electrical elements outside the TSV hole, causing failures of the electrical elements.
Data Source
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AI summary
Provided are a chip and a memory, relating to the technical field of semiconductors, and intended to solve the technical problem of low qualification rate of chips. The chip includes a base in which a through hole penetrating through the base is provided. A conductive column is provided in the through hole. A first surface of the base is provided with a first annular groove which surrounds the conductive column. A first isolator is provided in the first annular groove, and a first air gap extending along a circumferential direction of the first annular groove is formed in the first isolator. When generated between the conductive column and the base, a thermal stress is released by the first air gap in the first isolator, thereby alleviating or avoiding lattice deformation in the base outside the first annular groove, relieving local delamination of the chip, alleviating influence of the thermal stress on electrical elements on the chip, reducing failure of the electrical elements, and further improving the qualification rate of the chip.