Copper-Doped Via Metallization With Graded Dopant Interfaces
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Solution Overview
Problem
Copper voids at interfaces in semiconductor vias lead to high resistance and failure, with existing processes either reducing voids at the expense of increased resistance in interconnects or failing to maintain low resistivity.
Innovation Solution
A method involving the deposition of a copper layer with a high dopant content, followed by annealing to migrate the dopant towards the dielectric interface, and subsequent deposition of a low dopant content copper layer to fill the vias, ensuring improved interface quality and low resistivity through a two-part copper process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper voids are reduced at interfaces, then reliability is improved, but resistivity increases
Solution Approach 1:
The patent applies local quality by creating a graded dopant distribution where the first copper layer has high dopant content (0.5-10%) at the via interface to prevent voids and improve reliability, while the second copper layer has low or zero dopant content (0-0.5%) in the bulk interconnect region to maintain low resistivity. This spatial variation in dopant concentration optimizes both interface quality and electrical performance.
Solution Approach 2:
The copper interconnect is segmented into two distinct layers: a first copper layer deposited with high dopant content specifically at the via interface region, and a second copper layer with low dopant content for the bulk interconnect. This segmentation allows each layer to fulfill its specific function - the first layer prevents voiding at the critical interface, while the second layer ensures low overall resistivity.
2Reliability
If dopant content is increased to improve interface quality, then reliability is improved, but resistivity increases
Solution Approach 1:
The patent implements local quality by concentrating high dopant content (0.5-10%) in the first copper layer at the via interface where electro migration resistance is critical, while maintaining low dopant content (0-0.5%) in the second copper layer for the bulk interconnect where low resistivity is paramount. This localized dopant distribution achieves improved electro migration performance without sacrificing overall electrical conductivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electro migration and time-dependent dielectric breakdown performance, allows scaling to sub-30 nm pitch, and maintains low resistivity in interconnects by optimizing dopant distribution at interfaces and in bulk areas.
Implementation Method 1
depositing a first copper layer with a dopant with a first dopant content on a feature on a substrate by sputtering a first copper-based target at a first temperature
Implementation Method 2
annealing the substrate at a second temperature to reflow the first copper layer on the substrate to migrate the dopant in the first copper layer towards a dielectric interface
Implementation Method 3
annealing the substrate at a second temperature to reflow the first copper layer on the substrate to migrate the dopant in the first copper layer towards a dielectric interface
Data Source
AI summary
Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.