Copper Wiring Impurity Profiles for TDDB and SIV Control
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Solution Overview
Problem
Semiconductor devices with copper wiring face issues of decreased breakdown voltage and Time Dependent Dielectric Breakdown (TDDB) lifetime in narrow wiring due to copper ion migration, and Stress Induced Void (SIV) in wide wiring, which existing technologies fail to address simultaneously.
Innovation Solution
The semiconductor device features metal wirings with different widths, where the concentration of an impurity metal increases from the center to the surface in narrow wirings and decreases from the bottom to the surface in wide wirings, formed using a sputtering method and subsequent annealing, to suppress copper ion migration and manage SIV without increasing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If copper is used as wiring material to achieve low resistance, then electrical conductivity is improved, but copper ion migration occurs at interfaces causing decreased breakdown voltage and TDDB lifetime
Solution Approach 1:
The patent applies local quality by creating a non-uniform concentration distribution of impurity metals within the copper wiring. Specifically, the impurity concentration varies from the center to the surface of the wiring, with higher concentration at the surface where copper ion migration occurs. This localized variation in composition provides different functional properties: the high impurity concentration at the surface suppresses copper ion migration and improves interface stability, while the copper-rich center maintains low electrical resistance.
Solution Approach 2:
The patent employs parameter changes by systematically varying the concentration of impurity metals (such as aluminum, silicon, or nickel) within the copper wiring structure. The impurity concentration is controlled to range from 0.1-10 at% at the surface to lower concentrations at the center. This parameter variation allows the wiring to simultaneously achieve suppression of copper ion migration at the interface and maintenance of low bulk resistance, resolving the contradiction between reliability and conductivity.
2Reliability
If impurity concentration is increased in copper wiring to suppress copper ion migration, then breakdown voltage and TDDB lifetime are improved, but resistance of the wiring increases
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially differentiated impurity distribution. The impurity concentration is designed to be high (0.1-10 at%) at the surface region where copper ion migration occurs, providing local suppression of ion migration and improved interface reliability. Meanwhile, the center region maintains low impurity concentration to preserve low electrical resistance. This localized approach allows the system to achieve reliability improvement without significant resistance penalty.
Solution Approach 2:
The patent applies partial action by introducing impurity metals only in the specific region where they are needed (the surface/interface region) rather than uniformly throughout the entire wiring. The impurity concentration is controlled to be excessive only where required for migration suppression, while maintaining copper purity in the bulk region for optimal conductivity. This partial application of impurity addition minimizes the overall impact on resistance while achieving the desired reliability improvement.
3Reliability
If uniform impurity distribution is used in all wiring to prevent copper ion migration, then narrow wiring reliability is improved, but wide wiring experiences unnecessary resistance increase and SIV
Solution Approach 1:
The patent applies local quality by creating different impurity concentration profiles tailored to specific wiring types. For narrow wiring, the impurity concentration is designed to increase from center to surface, providing strong suppression of copper ion migration. For wide wiring, the impurity concentration is kept lower overall and more uniformly distributed, preventing unnecessary resistance increase and SIV formation. This spatial and contextual differentiation of impurity distribution allows the system to optimize performance for different wiring geometries.
Solution Approach 2:
The patent employs dynamics by making the impurity concentration profile adaptable to different wiring conditions. The concentration distribution is not fixed but is designed to vary based on wiring width and application requirements. This dynamic approach allows the same copper alloy system to provide optimal performance across different wiring geometries, with higher surface concentrations for narrow wiring needing migration suppression and lower overall concentrations for wide wiring where SIV is the concern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively improves breakdown voltage in narrow wirings and reduces the occurrence of SIV in wide wirings, preventing the decrease in TDDB lifetime while maintaining acceptable resistance levels.
Implementation Method 1
depositing a conduction film where a conduction material containing copper to which platinum etc. is added is deposited by a sputtering method
Implementation Method 2
manufacturing method includes forming a first seed alloy film containing copper and an impurity metal which is different from copper by using a sputtering method to embed a part of the grooves, planarizing the film thickness of the first seed alloy film at the side wall of the grooves by etching the first seed alloy film, forming a second seed alloy film containing copper and the impurity metal by using a sputtering method over the first seed alloy film to embed a part of the grooves, forming a plated metal layer containing copper as a main component over the second seed alloy film to embed the other part of the grooves, annealing the first seed alloy film, the second seed alloy film, and the plated metal film
Data Source
AI summary
A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.