Coprocessor Cache Invalidation Without Remote Instruction Execution
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Solution Overview
Problem
Existing processor implementations face challenges in securely and efficiently invalidating data in remote caches, particularly in coprocessors that are not managed by coherence circuitry, leading to potential security risks and performance issues.
Innovation Solution
A primary processor executes a remote invalidate instruction to directly command a coprocessor's invalidation control circuitry to invalidate cache lines at fine granularity, bypassing execution on the coprocessor, ensuring secure and efficient cache line-level invalidation without executing instructions on the coprocessor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based invalidation is used in coprocessor caches, then invalidation can be performed, but security risks and performance issues arise
Solution Approach 1:
The patent replaces software-based invalidation mechanisms with hardware-based invalidation control circuitry. The primary processor sends invalidate commands directly to the coprocessor's invalidation control circuitry, which automatically invalidates cache lines without requiring software execution. This hardware substitution eliminates security vulnerabilities associated with software-based approaches while improving invalidation performance.
Solution Approach 2:
The patent introduces an invalidation control circuitry as an intermediary component between the primary processor and the coprocessor cache. This intermediary receives invalidate commands from the primary processor and directly manages cache line invalidation in the coprocessor, eliminating the need for software-based coordination and reducing both security risks and performance overhead.
2Device complexity
If coarse-grained cache invalidation is performed, then implementation is simpler, but interference with other cached data increases and performance decreases
Solution Approach 1:
The patent implements fine-grained cache invalidation by dividing the cache invalidation process into individual cache line segments. The invalidation control circuitry receives invalidate commands that specify particular cache line addresses and only invalidates those specific lines rather than flushing the entire cache. This segmentation allows precise control over which data is invalidated, minimizing interference with other cached data and maintaining high cache utilization performance.
3Ease of operation
If coprocessor executes invalidation instructions, then invalidation can be performed, but execution time and performance overhead increase
Solution Approach 1:
The patent implements a self-service invalidation mechanism where the coprocessor's invalidation control circuitry automatically handles cache line invalidation without requiring the coprocessor to execute instructions. The primary processor sends invalidate commands directly to the invalidation control circuitry, which autonomously performs the invalidation operation. This eliminates the time overhead associated with instruction fetch, decode, and execution while maintaining the ability to perform targeted invalidation.
Data Source
AI summary
Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.