Coprocessor Cache Line Tracking for VM Migration

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Solution Overview

Problem

Conventional live migration of virtual machines (VMs) is time-consuming due to page-level granularity tracking, limiting the ability to host large databases and high-performance computing workloads in cloud environments.

Innovation Solution

A system with a host processor and a coprocessor that tracks cache line state, allowing for independent monitoring and reduced data transfer, enabling VM state migration at increased speeds by tracking clean versus dirty memory bits at the cache line granularity level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If page-level granularity tracking is used in conventional live migration, then the migration process is simple to implement, but the migration time is very long and productivity is reduced

Engineering Contradiction:

Improvemigration speedVSAvoidmigration time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent segments the memory tracking granularity from page-level to cache line-level (64 bytes). By dividing the memory into smaller cache line units and tracking only modified cache lines within each page, the system reduces the amount of data that needs to be transferred during migration, thereby increasing migration speed and productivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of tracking by implementing dirty bit tracking at the cache line level within each page. This additional granularity dimension allows the system to identify and transfer only the specific modified cache lines rather than entire pages, significantly reducing transfer time and improving productivity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If page-level granularity tracking is used, then the implementation is straightforward, but the data transfer volume is excessive and loss of substance increases

Engineering Contradiction:

Improvedata transfer volumeVSAvoidredundant data transfer

Core Design Contradiction:

Quantity of substanceVSLoss of substance

Solution Approach 1:

The patent extracts and identifies only the modified cache lines within each page using dirty bits, separating them from the unchanged portions. This extraction principle allows the migration system to transfer only the necessary modified data (dirty cache lines) rather than entire pages, reducing data transfer volume and eliminating redundant transfers.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of transferring complete pages (excessive action), the patent implements partial action by transferring only the modified cache lines within each page. This partial transfer approach reduces the quantity of data transferred while ensuring all necessary changes are migrated, thereby reducing loss of substance.

Inventive Principle:

Principle #16Partial or excessive action

3Productivity

If cache line granularity tracking is implemented, then migration speed increases and productivity improves, but device complexity increases due to coprocessor requirements

Engineering Contradiction:

Improvemigration speedVSAvoidsystem architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a coprocessor as an intermediary component that handles the complex cache line tracking and dirty bit management. This intermediary device offloads the complexity from the main migration system, enabling fine-grained cache line tracking and improved migration speed while isolating the complexity within a dedicated hardware component.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If iterative page migration is performed until dirty page threshold is reached, then reliability is maintained, but loss of time increases and productivity decreases

Engineering Contradiction:

Improvemigration completenessVSAvoidmigration efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary action by pre-tracking and marking dirty cache lines within each page before migration. This preliminary tracking allows the system to identify all modified data in advance, enabling more efficient migration planning and execution while ensuring no data is missed, thereby maintaining reliability while improving productivity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11809899B2Methods and apparatus for accelerating virtual machine migration

Publication Date: 2023.11.07 ALTERA CORP

AI summary

A server having a host processor coupled to a programmable coprocessor is provided. One or more virtual machines may run on the host processor. The coprocessor may be coupled to an auxiliary memory that stores virtual machine (VM) states. During live migration, the coprocessor may determine when to move the VM states from the auxiliary memory to a remote server node. The coprocessor may include a coherent protocol home agent and state tracking circuitry configured to track data modification at a cache line granularity. Whenever a particular cache line has been modified, only the data associated with that cache line will be moved to the remote server without having to copy over the entire page, thereby substantially reducing the amount of data that needs to be transferred during migration events.