Coprocessor Cache Invalidation via Remote Processor Commands
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Solution Overview
Problem
Existing processor implementations face challenges in securely and efficiently invalidating data in coprocessor caches, particularly when coherence circuitry is not present, leading to potential security risks and performance issues with software-based invalidation methods.
Innovation Solution
A primary processor executes a remote invalidate instruction to directly command coprocessor cache invalidation control circuitry, allowing for secure and fine-grained invalidation at cache line granularity without executing instructions on the coprocessor, using a bus command to manage cache lines in the coprocessor cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software-based invalidation methods are used for coprocessor caches, then the coprocessor can invalidate its own cache, but security risks increase and performance decreases due to interference with other cached data
Solution Approach 1:
The patent introduces an intermediary invalidation command mechanism where the primary processor sends targeted invalidation commands to the coprocessor cache control circuitry. This intermediary approach allows the primary processor to securely invalidate specific cache lines without executing instructions on the coprocessor, thus maintaining security while achieving precise cache invalidation.
2Ease of operation
If software-based invalidation methods are used for coprocessor caches, then the coprocessor can invalidate its own cache, but performance decreases due to interference with other cached data
Solution Approach 1:
The patent segments the cache invalidation process into fine-grained cache line级别的 operations. Instead of invalidating entire cache sets or relying on broad software mechanisms, the system invalidates individual cache lines targeted by the primary processor, minimizing interference with other cached data and improving overall system performance.
Solution Approach 2:
The patent applies local quality by enabling targeted invalidation of specific cache lines rather than uniform invalidation approaches. The primary processor can selectively invalidate only the cache lines that need to be invalidated, leaving other cached data intact, thus maintaining high system performance while achieving the required cache invalidation.
3Reliability
If coherence circuitry is used to manage cache invalidation, then cache contents remain up to date, but coprocessor caches not managed by coherence circuitry cannot be invalidated
Solution Approach 1:
The patent implements a universal invalidation command mechanism that works across different cache types and management approaches. The primary processor can send invalidation commands to coprocessor caches regardless of whether they are managed by coherence circuitry or not, making the invalidation mechanism universally applicable to all cache scenarios in the system.
Solution Approach 2:
The patent introduces an intermediary invalidation command interface between the primary processor and coprocessor caches. This intermediary mechanism bridges the gap for caches not managed by coherence circuitry, allowing the primary processor to directly invalidate cache lines in coprocessor caches through bus commands, thus extending cache management coverage to all coprocessor caches.
Data Source
AI summary
Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.