Co-Processor Chain Frame Control for Fast Task Switching
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Solution Overview
Problem
Existing co-processors face inefficiencies in performing a sequence of different processing operations due to the need for frequent reconfiguration of parameter registers, which is costly and inefficient.
Innovation Solution
A co-processor design featuring a plurality of processing circuits, a first memory for control data, and a second memory for storing a chain frame specifying a sequence of processing operations, with a Finite-State Machine (FSM) to manage the execution of these operations, allowing seamless transition between different processing tasks without repeated reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a co-processor uses a configurable processing circuit to perform different processing operations, then the adaptability of the system is improved, but the device complexity and reconfiguration overhead increase
Solution Approach 1:
The processing system is divided into multiple independent processing circuits (first processing circuit, second processing circuit, etc.), each capable of performing specific processing operations. Instead of reconfiguring a single configurable circuit, the system segments functionality across multiple dedicated circuits, eliminating reconfiguration overhead while maintaining adaptability through selective activation of different circuits based on operation type.
2Adaptability or versatility
If parameter registers are reconfigured frequently to execute different processing operations, then the versatility of the co-processor is improved, but the productivity and execution efficiency deteriorate
Solution Approach 1:
Multiple processing circuits are pre-configured with different processing functionalities before execution begins. The control logic pre-loads the appropriate processing circuit based on the operation type, eliminating the need for time-consuming reconfiguration during operation execution. This preliminary preparation of processing resources maintains versatility while preserving execution efficiency.
3Device complexity
If a single configurable processing circuit is used, then the device complexity is reduced, but the productivity and speed of executing different processing operations deteriorate
Solution Approach 1:
The system implements dynamic selection and activation of processing circuits based on the type of operation required. While multiple processing circuits exist in the architecture, only the necessary circuit is activated for each specific task, creating a dynamic resource allocation strategy that balances device complexity with processing speed and efficiency.
4Adaptability or versatility
If manual reconfiguration of parameter registers is performed for each processing operation, then the adaptability is improved, but the ease of operation and automation level deteriorate
Solution Approach 1:
The control logic automatically selects and activates the appropriate processing circuit based on the operation type without requiring manual reconfiguration. The system serves itself by autonomously managing the selection of processing resources, improving both the ease of operation and the extent of automation while maintaining the ability to perform diverse processing operations.
Data Source
AI summary
A co-processor comprises a plurality of processing circuits, a finite-state machine (FSM), a first memory, and a second memory. The first memory is configured to store control data, and the second memory comprises a memory area for storing a chain frame specifying a sequence of one or more processing operations, wherein the data associated with each processing operation comprise a code indicating one of the processing circuits and a configuration data frame comprising configuration data to be used for the processing operation. Specifically, the FSM is configured to determine whether the processing chain should be processed based on the control data, determine the code associated with a given processing operation indicated by a frame pointer, and enable the respective processing circuit. Conversely, the enabled processing circuit is configured to read the respective configuration data frame, and execute the respective processing operation.