Coprocessor Clock Mesh Gating for Mixed 128/256-Bit Pipelines
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Solution Overview
Problem
Processing systems with coprocessors face inefficiencies in power consumption and signal propagation delays due to the need to provide clock signals to all 256 bits, even when only 128 bits are used, and the unnecessary reading and writing of zeros in the high 128 bits for 128-bit instructions.
Innovation Solution
Implementing separate clock meshes for the low and high 128 bits of a pipeline and using a 'zero high' bit to indicate when the high bits are zero, allowing the scheduler to set them to zero and reducing the need for reading from the physical register file, thereby conserving power and optimizing clock signaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock signals are provided to all 256 lanes of the pipeline, then the coprocessor can execute 256-bit instructions, but power is unnecessarily consumed to clock the high 128 bits when only 128-bit instructions are used
Solution Approach 1:
The pipeline is divided into two separate clock meshes: a first clock mesh for the low 128 bits and a second clock mesh for the high 128 bits. This segmentation allows independent control of clocking to each segment, enabling the system to clock only the necessary portion (low 128 bits) when executing 128-bit instructions, thereby reducing power consumption while maintaining support for both 128-bit and 256-bit instructions
Solution Approach 2:
The clock meshes are made dynamically controllable through a state machine that monitors the retirement queue and adjusts clock mesh operation accordingly. When no 256-bit instructions are in flight, the second clock mesh is turned off; when 256-bit instructions are detected, the second clock mesh is activated. This dynamic adaptation resolves the contradiction between versatility and power consumption
2Ease of operation
If the high 128 bits are read from and written to the physical register file for 128-bit instructions, then the register file operates uniformly, but unnecessary power is consumed and signal propagation delays increase
Solution Approach 1:
The unnecessary operation of reading and writing zero values to the high 128 bits in the physical register file is extracted and eliminated. The system uses a 'zero high' bit indicator to detect when high bits are zero, allowing the scheduler to bypass the register file for these bits and directly set them to zero, thereby reducing power consumption and eliminating unnecessary signal propagation delays while maintaining uniform register file operation for cases where high bits are non-zero
3Adaptability or versatility
If additional data paths are provided for 256 bits, then the coprocessor supports wider instructions, but signal propagation delays increase due to physical constraints
Solution Approach 1:
The data paths are segmented into two separate clock meshes with different operational characteristics. The first clock mesh handles the low 128 bits with faster timing, while the second clock mesh handles the high 128 bits with extended timing when activated. This segmentation allows the system to support 256-bit instructions through additional data paths while managing signal propagation delays by only activating the slower second mesh when 256-bit instructions are actually being executed
Data Source
AI summary
A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.