Co-processor Architecture for DCNN Power Efficiency
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Solution Overview
Problem
Current computing architectures for artificial vision systems, particularly those using deep convolutional neural networks (DCNNs), face challenges in achieving real-time processing and efficiency while maintaining low power consumption, especially in mobile and lightweight platforms like micro-UAVs and mobile robots, due to high computational costs and memory bottlenecks.
Innovation Solution
A novel concurrent programmable data co-processor architecture that includes a memory router and collection blocks with programmable operators, allowing for efficient data transfer and parallel processing within shared memory, eliminating the need for a host computer and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional computing architectures with host computers and PCI connections are used for DCNN processing, then computational power can be achieved, but power consumption becomes significantly high and the system cannot be embedded in mobile platforms
Solution Approach 1:
The system is segmented into distinct functional blocks: a processing system (host) and a coprocessor with dedicated processing elements, memory interface, and collection blocks. This segmentation allows the computationally intensive DCNN operations to be offloaded to the coprocessor while the host handles control and data management, distributing the power consumption burden and enabling mobile deployment.
Solution Approach 2:
A coprocessor acts as an intermediary between the host computer and the processing elements. It includes a memory interface that manages data transfer between external memory and processing blocks, and collection blocks that aggregate results. This intermediary handles the computationally expensive operations locally, reducing the need for continuous host-coprocessor communication and lowering overall system power consumption.
2Speed
If FPGAs with host computers are used for hardware-accelerated vision systems, then processing speed improves, but the system requires large off-chip memories and suffers from communication bottlenecks over PCI
Solution Approach 1:
The coprocessor architecture merges the processing elements, memory interface, and collection blocks into a single integrated unit. The memory interface is directly coupled to external memory, eliminating the need for large off-chip memories separate from the processing unit. This integration reduces communication bottlenecks by providing direct memory access to processing elements without requiring PCI bus transactions for every data transfer.
Solution Approach 2:
The architecture introduces a new dimension of parallelism through multiple collection blocks that can operate simultaneously. Each collection block handles specific data streams or processing streams independently, allowing parallel data aggregation and reducing the communication burden on the host. This multi-dimensional approach to data flow management increases processing throughput without proportionally increasing memory requirements.
3Measurement precision
If deep convolutional neural networks with multiple layers and hundreds of filters are implemented, then feature extraction accuracy improves, but computational cost increases significantly
Solution Approach 1:
The coprocessor performs preliminary computational actions by pre-processing and filtering data streams before they reach the host system. Collection blocks aggregate intermediate results from multiple processing elements, performing partial computations in advance. This preliminary action reduces the computational burden on the host and allows the system to handle deeper DCNN layers with more filters without proportionally increasing overall computational cost.
Solution Approach 2:
The architecture enables continuous processing through pipelined operation of processing elements and collection blocks. Data flows continuously through the system with multiple stages operating in parallel, maintaining high utilization of computational resources. This continuous action allows the system to process multiple DCNN layers sequentially without idle time, improving computational efficiency while maintaining the accuracy benefits of deep networks.
Data Source
AI summary
A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.