Coprocessor Event Detection Circuit for Error Injection Security

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Solution Overview

Problem

Existing methods for detecting error injection attacks on coprocessors in secured integrated circuits, such as those in smart cards, are inadequate as they either require repetitive calculations, which increase processing time, or can be bypassed by sophisticated error injection techniques, particularly in hard-wired logic coprocessors that do not execute code-instructions.

Innovation Solution

A method that puts the coprocessor into an error mode by default at the start of command execution, monitors for execution errors, and declares an error mode to the external environment if suspicious events occur, such as attempts to access registers, using an error detection circuit and event detection circuit to ensure secure operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If repetitive calculations are used to detect error injection attacks, then detection reliability is improved, but processing time increases

Engineering Contradiction:
Improvedetection reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by setting the coprocessor into an error mode by default at the beginning of command execution. This pre-configured state enables continuous monitoring for execution errors without requiring repetitive calculations after the fact. The error detection circuit continuously compares actual execution results against expected values, allowing timely detection of error injection attacks while maintaining efficient processing time.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If classical error detection methods are used on hard-wired logic coprocessors, then detection capability is improved, but the methods can be bypassed by sophisticated error injection techniques

Engineering Contradiction:
Improvedetection capabilityVSAvoiderror injection bypass
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements feedback by continuously monitoring the execution of commands and comparing actual results against expected values. The error detection circuit receives feedback signals from the calculation unit and control unit, enabling real-time detection of deviations caused by error injection attacks. This feedback mechanism ensures that sophisticated error injection techniques cannot bypass detection, as any deviation from expected execution patterns is immediately detected and reported.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If redundant data paths are used for error detection, then detection precision is improved, but device complexity increases

Engineering Contradiction:
Improvedetection precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the error detection circuit to serve multiple functions: it monitors execution errors, detects error injection attacks, and provides feedback to both the control unit and external environment. Rather than adding separate redundant data paths for every possible detection scenario, the circuit leverages existing signal paths and control mechanisms, achieving comprehensive detection precision without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8359481B2Secured coprocessor comprising an event detection circuit
Publication Date: 2013.01.22 STMICROELECTRONICS FRANCE
  • US8359481B2 patent drawing
  • US8359481B2 patent drawing
  • US8359481B2 patent drawing

AI summary

A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.