Coprocessor Instruction Suppression for Execution Performance

Solution Overview

Problem

The existing coprocessor synchronization mechanisms, which use 'set' and 'clear' instructions to manage coprocessor sequences, can reduce performance and efficiency due to the barrier effect caused by these instructions, especially in cases of short sequences with few instructions.

Innovation Solution

The suppression of the execution of 'clear' and 'set' instructions when they are adjacent in the instruction buffer or queue, allowing out-of-order execution of coprocessor instructions while ensuring correct initialization and invalidation of the coprocessor state through the use of a color-based scheme to manage dependencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronizing instructions (set and clear) are executed to manage coprocessor sequences, then coprocessor state initialization and invalidation are ensured, but performance and efficiency are reduced due to the barrier effect

Engineering Contradiction:

Improvecoprocessor state managementVSAvoidexecution performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and removes redundant synchronizing instructions from the instruction sequence. When a clear instruction is immediately followed by a set instruction, the clear instruction is eliminated since the set instruction will reinitialize the state anyway. This extraction of unnecessary barrier instructions reduces the barrier effect while preserving the essential state management functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent discards redundant synchronizing instructions that serve no practical purpose. By identifying and removing clear instructions that are immediately followed by set instructions, the system recovers performance without sacrificing reliability, as the set instruction ensures proper state initialization regardless of whether the clear instruction executes.

Inventive Principle:

Principle #34Discarding and recovering

2Reliability

If synchronizing instructions are executed in order to ensure proper sequencing, then state initialization and invalidation are guaranteed, but execution time increases due to barrier effects

Engineering Contradiction:

Improveinstruction sequencingVSAvoidexecution time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and removes redundant synchronizing instructions from the instruction sequence. When a clear instruction is immediately followed by a set instruction, the clear instruction is eliminated since the set instruction will reinitialize the state anyway. This extraction of unnecessary barrier instructions reduces the barrier effect while preserving the essential state management functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

3Use of energy by moving object

If coprocessor sequences are kept short with few instructions, then power efficiency is improved, but the barrier effect of synchronizing instructions has a greater relative impact on performance

Engineering Contradiction:

Improvepower efficiencyVSAvoidexecution efficiency

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent extracts and removes redundant synchronizing instructions from the instruction sequence. When a clear instruction is immediately followed by a set instruction, the clear instruction is eliminated since the set instruction will reinitialize the state anyway. This extraction of unnecessary barrier instructions reduces the barrier effect while preserving the essential state management functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11650825B2Coprocessor synchronizing instruction suppression

Publication Date: 2023.05.16 APPLE INC

AI summary

An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.