Coprocessor Instruction Translation for CPU Load Reduction
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Solution Overview
Problem
Current coprocessor systems have limited usage due to differences in instruction sets between CPUs and coprocessors, leading to inefficient CPU load management and reduced coprocessor utilization, as they require separate compilation and cannot dynamically migrate tasks based on real-time CPU and memory usage.
Innovation Solution
A computer instruction processing method and system where a CPU can migrate instructions to a coprocessor running an operating system, allowing the coprocessor to execute instructions and reduce CPU load by using a translation table to convert incompatible binary codes, enabling dynamic task migration based on CPU and memory thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate compilation is used for CPU and coprocessor codes, then code execution compatibility is ensured, but coprocessor utilization is reduced and CPU load cannot be properly reduced
Solution Approach 1:
The patent introduces a translation layer that acts as an intermediary between CPU instructions and coprocessor instructions. When the CPU encounters a coprocessor instruction, it triggers a translation mechanism that converts the instruction into coprocessor-executable format, enabling dynamic task migration without requiring separate compilation processes.
Solution Approach 2:
The system dynamically determines at runtime which instructions should be executed by the coprocessor based on CPU load thresholds and instruction type analysis, rather than having fixed compilation decisions. This allows the system to adaptively migrate tasks to the coprocessor, improving utilization while maintaining compatibility.
2Ease of manufacture
If fixed task allocation is used between CPU and coprocessor, then compilation simplicity is maintained, but actual coprocessor usage is low and CPU load reduction is insufficient
Solution Approach 1:
The system implements dynamic task allocation based on runtime conditions such as CPU load thresholds and instruction analysis. The CPU monitors its own load and dynamically decides which tasks to migrate to the coprocessor, maintaining compilation simplicity while achieving effective load reduction.
Solution Approach 2:
The CPU continuously monitors its load and uses this feedback to determine when to migrate tasks to the coprocessor. When CPU load exceeds a threshold, the system automatically identifies suitable instructions for migration and transfers them, creating a closed-loop control system that optimizes load distribution.
3Device complexity
If no operating system is installed on the coprocessor, then system complexity is reduced, but task migration capability and coprocessor versatility are limited
Solution Approach 1:
The coprocessor is designed to run a full operating system, enabling it to execute independent processes and handle multiple tasks simultaneously. This multi-functionality allows the coprocessor to serve as both a simple co-processor and an independent processing node, greatly enhancing task migration capability and system versatility.
Solution Approach 2:
The system is segmented into two independent processing nodes (CPU and coprocessor), each capable of running its own operating system and managing its own processes. This segmentation enables autonomous task execution on the coprocessor while maintaining clear boundaries that manage system complexity.
Data Source
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AI summary
Embodiments of the present invention disclose a computer instruction processing method, a coprocessor, and a system. The computer instruction processing method includes: receiving, by a coprocessor, a first instruction set migrated by a central processing unit CPU; acquiring, according to the first instruction set that is applicable to the CPU for execution, a second instruction set for execution in the coprocessor; and executing binary codes in the second instruction set. In this way, the coprocessor that executes the second instruction set substitutes for the CPU that executes the first instruction set, CPU load is reduced, and usage of the coprocessor is improved.