Coprocessor Interrupt Deadlock Avoidance via State Retention
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Solution Overview
Problem
In processor systems with coprocessors, interrupt processing during coprocessor instruction execution can lead to deadlock situations due to resource mismatches, particularly when address generation parameters need to be reset, complicating control programs and reducing processing efficiency.
Innovation Solution
A deadlock avoidance method that involves issuing a cancellation request for the coprocessor instruction, determining its execution state, and either canceling or suspending it, allowing immediate interrupt processing to reset and restore the execution state, thereby avoiding deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt processing is executed after waiting for coprocessor instruction to end, then resource mismatch is avoided, but deadlock occurs and processing efficiency decreases
Solution Approach 1:
The system performs preliminary actions by saving the execution state of the coprocessor instruction before interrupt processing begins. This allows the interrupt to be handled immediately without waiting for the coprocessor instruction to complete, while the saved state ensures resource mismatch is prevented when the instruction is resumed or canceled.
Solution Approach 2:
The system dynamically adjusts the handling of coprocessor instructions based on the cancellation request. By determining whether to cancel or suspend the instruction and managing execution states flexibly, the system can immediately process interrupts while maintaining resource consistency, resolving the deadlock situation.
2Reliability
If coprocessor instruction execution is continued until completion, then resource mismatch is prevented, but deadlock situation arises and processing efficiency is reduced
Solution Approach 1:
The execution state is saved in advance before interrupt processing starts. This preliminary action enables the system to immediately handle interrupts without delaying them until the coprocessor instruction completes, while the saved state ensures resource consistency is maintained when the instruction is resumed or canceled.
Solution Approach 2:
The system extracts the execution state information from the ongoing coprocessor instruction and separates it into a saved state that can be independently managed. This allows the interrupt processing to proceed independently without blocking, while the extracted state information ensures resource consistency when the original instruction is resumed.
3Adaptability or versatility
If data transfer parameter is reset during coprocessor instruction execution, then address generation is updated, but control program becomes complicated and deadlock may occur
Solution Approach 1:
The execution state is saved before the parameter reset operation begins. This allows the data transfer parameter to be reset during coprocessor instruction execution without complicating the control program, as the saved state ensures that resource mismatches are prevented when the instruction is resumed or canceled.
Solution Approach 2:
The saved execution state acts as an intermediary that mediates between the interrupt processing and the coprocessor instruction. It allows the data transfer parameter to be reset flexibly while maintaining resource consistency, simplifying the control program by providing a clear mechanism for state management during parameter changes.
Data Source
AI summary
A processor core interrupt control circuit issues a request signal for requesting cancellation of a coprocessor instruction being executed at a coprocessor. A program control circuit issues interrupt processing after issuance of the cancellation request. A coprocessor computation control circuit retains the execution state of the coprocessor instruction. Upon receiving the processing cancellation request signal, a coprocessor interrupt control circuit performs cancellation or holding of the coprocessor instruction on the basis of execution state information retained by the coprocessor computation control circuit. The coprocessor interrupt control circuit evicts the execution state of the coprocessor instruction in the case of holding, and restores the execution state of the coprocessor instruction that had been evicted after completion of the interrupt processing.