Coprocessor Memory Access via Communications Unit
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Solution Overview
Problem
In computing systems, the need to keep a main processor in a fully operational mode to process memory commands from coprocessors leads to delays and increased power consumption, especially when the main processor is in a reduced power mode, and implementing a second memory for coprocessors increases system cost and circuit board size.
Innovation Solution
A system with a host processor, communications unit, and coprocessor that allows the coprocessor to access a secure area of memory while the host processor is in a reduced power mode, using a communications unit to verify the coprocessor's identity and grant access, enabling data copying to a local memory without activating the host processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the main processor is kept in a fully operational mode to process memory commands from coprocessors, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The memory system is segmented into a first memory (accessible only when host processor is active) and a second memory (accessible by coprocessors independently). This segmentation allows coprocessors to access the second memory without activating the host processor, reducing power consumption while maintaining memory access capability.
Solution Approach 2:
A communications unit acts as an intermediary between coprocessors and the memory system. It verifies coprocessor identities and grants access to the second memory area without requiring the host processor to be active, enabling fast memory access while keeping the host processor in reduced power mode.
2Loss of time
If a second memory is added for coprocessor use, then memory access delays are eliminated, but system cost and circuit board size increase
Solution Approach 1:
The patent merges the first and second memories into a single shared memory system with differentiated access rights. The second memory area is a portion of the same memory structure as the first memory, but accessible under different conditions (coprocessor identity verification). This merging approach eliminates the need for completely separate memory hardware, reducing system cost and size while still providing fast access for coprocessors.
3Reliability
If the host processor is activated to process memory commands, then memory access reliability is improved, but processing delays occur when host is in reduced power mode
Solution Approach 1:
The system performs preliminary setup by creating a second memory area specifically for coprocessor use and configuring the communications unit to verify coprocessor identities. This preliminary configuration enables coprocessors to independently access memory without requiring host processor activation, eliminating recovery delays while maintaining reliable access through identity verification.
Data Source
AI summary
A system, a method, and an apparatus are disclosed. In an embodiment, a system includes a host processor with a communications unit, a memory coupled to the communications unit, and a coprocessor coupled to the communications unit. The memory may include at least a first area and a second area. The coprocessor may be configured to request access to the first area of the memory via the communications unit. The communications unit may be configured to verify an identity of the coprocessor, and grant access to the first area of the memory responsive to a positive identification of the coprocessor.