Coprocessor Memory Mapping to Non-Volatile Memory via System Block
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Solution Overview
Problem
The existing data transfer methods between coprocessors and non-volatile memory in computing devices suffer from significant overheads due to redundant memory allocations, data copies, and mode switching, leading to increased latency and reduced performance.
Innovation Solution
A computing device and method that maps coprocessor memory to a system memory block, allowing direct data transfer between the coprocessor and non-volatile memory through a controller driver and library, utilizing memory-mapped registers and pinned memory spaces, connected via protocols like NVMe and AHCI, to reduce overheads and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between coprocessor and non-volatile memory through traditional memory allocation and copying methods, then data transfer can be achieved, but significant overheads occur due to redundant memory allocations, data copies, and mode switching
Solution Approach 1:
The patent extracts the data transfer operation from the traditional CPU-managed memory allocation and copying process. By introducing a memory-mapped register that directly maps coprocessor memory to system memory, the data transfer path is separated from the CPU's memory management overhead, eliminating redundant allocations and copies while maintaining transfer capability.
Solution Approach 2:
The patent introduces a memory-mapped register as an intermediary between the coprocessor memory and system memory. This register acts as a mediator that enables direct access and transfer between the two memory spaces without requiring CPU intervention for each data movement operation, thus reducing mode switching overhead and latency.
2Volume of moving object
If the coprocessor uses on-board memory, then fast access is achieved, but the memory size is relatively smaller compared to host memory
Solution Approach 1:
The patent merges the coprocessor's on-board memory with the host system's large memory capacity through memory mapping. The coprocessor memory is mapped to a system memory block, creating a unified address space that combines the fast access characteristics of on-board memory with the large capacity of host memory, allowing the coprocessor to access both local and remote memory efficiently.
Solution Approach 2:
The patent extends the memory address space from the coprocessor's local dimension to the system's global memory dimension through mapping. By creating a virtual address space that spans both coprocessor memory and system memory, the patent allows access to large volumes of data while maintaining the speed characteristics of local memory access through the mapped interface.
3Device complexity
If kernel module directly accesses user-space memory, then data copy overhead can be reduced, but memory management and data copy overheads between kernel-space and user-space are unavoidable
Solution Approach 1:
The patent creates a virtual copy of the memory management interface through the memory-mapped register. Instead of requiring actual kernel-mode to user-space mode switching for each access, the mapped register provides a direct interface that replicates the appearance of direct access while operating within the coprocessor's address space, thus eliminating mode switching overhead while maintaining the illusion of direct access.
Data Source
AI summary
A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.