Coprocessor Real Address Access via Processor Translation

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Solution Overview

Problem

Modern computer systems face complexity and cost issues due to the need for address translation mechanisms in coprocessors, which are required to access memory, especially when handling multiple processors and asynchronous operations, leading to increased hardware complexity and management overhead.

Innovation Solution

A coprocessor accesses memory using real addresses generated by the processor's address translation mechanisms, with a coprocessor request block (CRB) containing real addresses for input and output operands, and hardware monitoring ensures data integrity and security by detecting changes in address context.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the coprocessor implements its own address translation mechanisms to access memory, then the coprocessor can independently access memory, but the hardware complexity and cost increase significantly

Engineering Contradiction:

Improvememory access capabilityVSAvoidaddress translation mechanisms

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The address translation functionality is extracted from the coprocessor and placed in the main processor. The coprocessor no longer needs its own address translation mechanisms, reducing its complexity. Instead, the coprocessor receives real addresses directly from the processor's address translation unit, separating the translation function from the coprocessor while maintaining its memory access capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The processor acts as an intermediary between the coprocessor and memory. The processor receives effective addresses from the coprocessor, translates them to real addresses through its address translation unit, and then accesses memory using the real addresses. This intermediary role eliminates the need for the coprocessor to implement complex address translation mechanisms while maintaining full memory access capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If multiple processors share a coprocessor, then resource utilization improves, but the management overhead and synchronization complexity increase

Engineering Contradiction:

Improveresource utilizationVSAvoidsynchronization mechanisms

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The address translation resources are merged into the processor rather than being duplicated in each coprocessor instance. Multiple processors can share the same address translation unit in the coprocessor, eliminating the need for each processor to maintain separate translation tables and synchronization mechanisms, thus reducing management overhead while improving resource utilization.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The coprocessor's address translation unit is designed to be universal, serving multiple processors simultaneously. Instead of being dedicated to a single processor, the translation mechanisms can handle address translation requests from any of the multiple processors, reducing the overall system complexity and improving resource utilization through multi-functionality.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If the coprocessor uses effective addresses to access memory, then address space isolation is maintained, but the coprocessor cannot directly access memory without processor intervention

Engineering Contradiction:

Improveaddress space isolationVSAvoidmemory access directness

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The processor performs preliminary address translation before the coprocessor accesses memory. The processor translates the coprocessor's effective addresses to real addresses in advance, allowing the coprocessor to directly access memory using the translated real addresses without requiring further processor intervention during the actual memory access operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The manual or software-based address translation process is replaced with hardware-based address translation in the processor's address translation unit. This hardware mechanism automatically translates effective addresses to real addresses, enabling the coprocessor to directly access memory while maintaining address space isolation, without requiring complex software intervention or sacrificing access directness.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP2616944B1Real address accessing in a coprocessor executing on behalf of an unprivileged process

Publication Date: 2016.06.08 INTERNATIONAL BUSINESS MACHINE CORPORATION

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AI summary

A coprocessor performs operations on behalf of processes executing in processors coupled thereto, and accesses data operands in memory using real addresses. A process executing in a processor generates an effective address for a coprocessor request, invokes the processor's address translation mechanisms to generate a corresponding real address, and passes this real address is the coprocessor. Preferably, the real address references a block of additional real addresses, each for a respective data operand. The coprocessor uses the real address to access the data operands to perform the operation. An address context detection mechanism detects the occurrence of certain events which could alter the context of real addresses used by the coprocessor or the real addresses themselves.