Coprocessor Register Data Saving via Single Acquisition Instruction

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Solution Overview

Problem

Existing information processing apparatuses with CPUs and coprocessors face inefficiencies in saving and restoring data from registers, particularly due to the need for multiple dedicated instructions as the number of registers increases, leading to a proliferation of instructions and potential unnecessary data saving.

Innovation Solution

An information processing apparatus with a CPU and coprocessor that uses a single acquisition instruction to specify and save data from multiple registers, utilizing a register number system and flag signals to manage data saving and restoration efficiently, allowing for the use of existing resources like flag registers for completion detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated extended calculation instruction is allotted to each register for saving data, then data saving and restoration can be performed, but the count of dedicated extended calculation instructions becomes too many

Engineering Contradiction:
Improvedata saving and restoration capabilityVSAvoidcount of dedicated extended calculation instructions
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single acquisition instruction that can operate on any register through parameter specification rather than creating dedicated instructions for each register. The instruction uses a register number field to identify the target register, allowing one instruction template to serve multiple registers, thereby reducing the total number of instructions while maintaining full data saving and restoration capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the parameter structure of the acquisition instruction by incorporating a register number parameter that dynamically identifies the source register. This parameter-driven approach allows the same instruction format to access different registers, eliminating the need for multiple hardcoded instructions and reducing instruction count while preserving functionality

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If the count of registers is increased to handle more calculations, then more data can be stored, but the count of dedicated extended calculation instructions will become too many

Engineering Contradiction:
Improvenumber of registersVSAvoidcount of instructions
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent makes the acquisition instruction universal by adding a register number parameter, allowing the same instruction to work with any number of registers. This enables the system to scale the number of registers without proportionally increasing the number of instructions, as the single instruction adapts to different register counts through parameter specification

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If data is saved from all registers during interruption, then no data is lost, but unnecessary data saving increases processing time

Engineering Contradiction:
Improvedata integrity during interruptionVSAvoiddata saving processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by enabling selective data saving based on register usage status. The system checks whether each register contains valid data before saving, and only saves registers that are actually in use. This localized approach to data saving maintains data integrity for relevant registers while avoiding the time waste of saving unused registers

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7877576B2Processing system having co-processor for storing data
Publication Date: 2011.01.25 PANASONIC SEMICON SOLUTIONS CO LTD
  • US7877576B2 patent drawing
  • US7877576B2 patent drawing
  • US7877576B2 patent drawing

AI summary

When an interruption instruction occurs in an information processing apparatus including a CPU and a coprocessor, execution of a single dedicated instruction “GETACX Dm,Dn” performs saving of necessary data from all registers. “Dm” is a value output from a general register group 104 to a first data input bus 120. Each of calculation units implemented in a coprocessor 110 recognizes a value stored therein. If a value “Dm” specifies one of the calculation units, the specified calculation unit outputs, to a selector 116, data stored in a register included in the specified calculation unit. An implemented calculation unit information output circuit 117 stores therein the count of the calculation units implemented in the coprocessor 110. If a value of the first data input bus 120 is greater than the count of the calculation units, the implemented calculation unit information output circuit 117 outputs a value “1” to a flag register 102. Based on the fact that the value stored on the flag register 102 is “1”, a CPU 100 recognizes that saving of the data from the register has been completed.