Coprocessor Synchronized Register Renaming for Stall Prevention

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Solution Overview

Problem

Microprocessors with multiple processing units face challenges in synchronized operation and resource management, leading to inefficiencies and potential stalls due to lack of resource synchronization between master processors and coprocessors.

Innovation Solution

A synchronized register renaming method is implemented, where the master processor sends operations to the coprocessor with an identifier, and the coprocessor schedules and executes them, notifying the master processor upon completion, while maintaining resource allocation maps to prevent stalls and ensure consistent resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the master processor sends operations to the coprocessor for execution, then the coprocessor can execute operations independently and out-of-order, but resource allocation desynchronization may cause stalls in the master processor

Engineering Contradiction:
Improveoperation execution throughputVSAvoidprocessor stall time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The coprocessor sends completion notifications back to the master processor using the identifier returned by the master processor. This feedback mechanism allows the master processor to track the status of outstanding operations and resume execution when resources become available, eliminating stalls caused by resource desynchronization.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The master processor allocates identifiers from a scheduler table in advance before operations are completed by the coprocessor. This preliminary allocation ensures that when operations complete, the master processor immediately has the identifiers needed to track and resume operations without waiting for resource availability notifications.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the coprocessor maintains resource allocation maps to track resources, then resource synchronization is improved, but the complexity of the coprocessor increases

Engineering Contradiction:
Improveresource synchronization accuracyVSAvoidcoprocessor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The coprocessor maintains an external resource allocation map that is a simplified copy or shadow of the actual resource allocation. This external map uses bit vectors to track resource availability in a compact form, providing the necessary synchronization information without requiring the full complexity of detailed resource tracking structures.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The resource allocation maps are implemented using bit vectors, which change the representation parameter from detailed resource descriptors to compact binary states. This parameter transformation reduces the complexity of storing and manipulating resource allocation information while maintaining the ability to track resource availability accurately.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7493471B2Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready
Publication Date: 2009.02.17 SUN MICROSYSTEMS INC
  • US7493471B2 patent drawing
  • US7493471B2 patent drawing
  • US7493471B2 patent drawing

AI summary

A method for synchronized renaming between a master processor and a coprocessor includes sending from the master processor an operation for execution by the coprocessor along with an identifier, at the coprocessor, renaming the operation for execution, including assigning a resource and associating the resource with the identifier, and at a subsequent time, sending the identifier from the master processor to the coprocessor to be used in conjunction with the execution of the renamed operation.