Coprocessor Logic Sector Reconfiguration via Stacked Memory
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Solution Overview
Problem
Programmable integrated circuits face challenges in reconfiguration speed, energy consumption, and parallel processing due to slow reconfiguration rates and high energy costs associated with on-chip caching and off-chip fetching of configuration bit-streams in datacenter applications.
Innovation Solution
A coprocessor integrated circuit with a secure device manager and logic sector managers dynamically allocates and reconfigures logic sectors using in-package stacked memory to optimize task execution, employing pre-configured sectors, load balancing, and efficient configuration data caching to enhance reconfiguration speed and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional reconfiguration methods are used to load configuration bit-streams, then the programmable device can be reconfigured to perform different functions, but the reconfiguration speed is several orders of magnitude slower than desired
Solution Approach 1:
The patent pre-loads configuration bit-streams into on-chip memory blocks before they are needed for reconfiguration. This preliminary action stores frequently used or predicted configuration data in fast on-chip memory, eliminating the need to fetch from slow off-chip storage during reconfiguration operations, thereby dramatically improving reconfiguration speed.
Solution Approach 2:
The patent divides the configuration bit-stream into multiple segments or chunks that can be independently loaded and stored in different on-chip memory blocks. This segmentation allows parallel loading and selective retrieval of configuration segments, enabling faster reconfiguration by only loading the necessary portions rather than entire configuration sets.
2Speed
If on-chip caching or buffering of prefetched configuration bit-streams is used to hide reconfiguration latency, then reconfiguration speed improves, but silicon real estate is undesirably expensive
Solution Approach 1:
The patent implements partial caching by storing only the most frequently used or predicted configuration bit-stream segments in on-chip memory, rather than caching entire configuration sets. This selective partial caching approach provides sufficient speed improvement for common reconfiguration scenarios while minimizing the silicon area consumed by on-chip memory.
Solution Approach 2:
The patent dynamically adjusts the amount of configuration data cached in on-chip memory based on usage patterns, prediction accuracy, and available memory resources. By changing the caching parameters adaptively, the system optimizes the balance between reconfiguration speed and silicon area utilization.
3Quantity of substance
If configuration bit-streams are fetched from off-chip storage via the entire configuration circuit chain, then configuration data can be loaded, but energy consumption is intensive
Solution Approach 1:
The patent pre-loads configuration bit-streams into on-chip memory during idle periods or when predicted to be needed soon, performing the energy-intensive transfer operation in advance rather than during active reconfiguration. This reduces the frequency of off-chip accesses and overall energy consumption.
Solution Approach 2:
The patent creates copies of frequently used configuration bit-streams and stores them in on-chip memory blocks. Instead of repeatedly fetching the same configuration data from off-chip storage, the system uses local copies, dramatically reducing the energy associated with data transfer through the configuration circuit chain.
4Adaptability or versatility
If the entire set of configuration data is loaded during reconfiguration, then the programmable device can be reconfigured, but the reconfiguration process is slow and energy-intensive
Solution Approach 1:
The patent segments the configuration bit-stream into multiple independent chunks or blocks that can be loaded and applied separately. This allows the reconfiguration process to load only the necessary segments rather than the entire configuration set, improving reconfiguration efficiency while maintaining full adaptability.
Solution Approach 2:
The patent implements partial reconfiguration by loading and applying only the specific configuration segments needed for the desired functionality, rather than loading the entire configuration data set. This partial action approach maintains adaptability while significantly improving reconfiguration speed and reducing energy consumption.
Data Source
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AI summary
A host processor may utilize a coprocessor to accelerate the performance of a task. Upon receiving a acceleration request from the host processor, the coprocessor may identify and select an available logic sector within the coprocessor that can be used to perform a task associated with the acceleration request. In some cases, the selected logic sector may not be configured to perform the task, in which case the selected logic sector may be reconfigured. The configuration bit stream used to reconfigure the selected logic sector to perform the task may be retrieved from a stacked memory die mounted on the coprocessor, or, if the configuration bit stream is not stored in the stacked memory die, the configuration bit stream may be retrieved from an external memory through the host processor. Load balancing may be performed to dynamically allocate additional logic sectors to time-critical tasks.