Coprocessor Slice Power Modes for Hybrid Core Efficiency
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Solution Overview
Problem
Current coprocessor designs in hybrid architectures lack the ability to dynamically adjust power management based on the specific core type running a service, leading to inefficiencies and inconsistencies in power consumption, as they do not account for performance-versus-power preferences of services or users.
Innovation Solution
A runtime connection is established between cores and coprocessors, allowing coprocessors to align their working modes with core modes on a per-slice basis, enabling dynamic power management that matches the requirements of performance or efficiency cores, thereby reducing total power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If coprocessor uses uniform power management for all cores, then device control is simplified, but power efficiency is reduced due to inability to match core performance preferences
Solution Approach 1:
The coprocessor is divided into multiple independent slices, each capable of operating in different power modes. This segmentation allows each slice to be independently controlled based on the performance requirements of the specific core it serves, resolving the contradiction between simplified control and power efficiency by enabling fine-grained power management without complex global control logic.
Solution Approach 2:
The coprocessor slices can dynamically transition between different power modes (performance mode and power-efficient mode) based on runtime conditions. This dynamic adaptability allows the system to optimize power consumption by switching modes according to the core's performance preferences while maintaining relatively simple control through predefined mode transitions.
2Use of energy by moving object
If coprocessor aligns working modes with core modes on per-slice basis, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The coprocessor is divided into multiple independent slices, each capable of operating in different power modes. This segmentation allows each slice to be independently controlled based on the performance requirements of the specific core it serves, resolving the contradiction between simplified control and power efficiency by enabling fine-grained power management without complex global control logic.
Solution Approach 2:
Each coprocessor slice autonomously determines its power mode based on the core type it is paired with, without requiring complex centralized control. The slice self-configures to match the performance preferences of its associated core, reducing the overall control complexity while achieving optimized power efficiency through decentralized decision-making.
3Ease of operation
If coprocessor forces uniform power status changes, then device control is simplified, but service performance preferences are not met
Solution Approach 1:
Different coprocessor slices are configured with different power mode capabilities based on the specific performance preferences of the services running on associated cores. This local quality approach allows each slice to have tailored power management characteristics that match its service requirements, maintaining ease of operation through standardized interfaces while achieving adaptability through customized local configurations.
Solution Approach 2:
The coprocessor slices can dynamically transition between different power modes (performance mode and power-efficient mode) based on runtime conditions. This dynamic adaptability allows the system to optimize power consumption by switching modes according to the core's performance preferences while maintaining relatively simple control through predefined mode transitions.
4Device complexity
If coprocessor operates without core type awareness, then device complexity is reduced, but power management consistency deteriorates
Solution Approach 1:
The coprocessor receives feedback information about the core type (performance core or efficiency core) running services and uses this feedback to automatically adjust the power mode of its slices. This feedback mechanism maintains power management consistency by ensuring the coprocessor adapts to the performance characteristics of the associated core without adding significant complexity, as the core type information is already available in the hybrid architecture.
Solution Approach 2:
Each coprocessor slice autonomously determines its power mode based on the core type it is paired with, without requiring complex centralized control. The slice self-configures to match the performance preferences of its associated core, reducing the overall control complexity while achieving optimized power efficiency through decentralized decision-making.
Data Source
AI summary
An accelerator apparatus can include an interface to receive service requests from at least one processing core. The accelerator apparatus can include coprocessor circuitry coupled to the interface and comprised of multiple slices. The coprocessor circuitry can detect a performance type for the at least one processing core. The coprocessor circuitry can operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core. Some operations can be alternatively performed by an operating system on any processor coupled to the network.