Central Processor Coprocessor Synchronization via Register Tagging
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Solution Overview
Problem
Current central processor-coprocessor synchronization schemes, such as polling and interrupts, require software overhead, which is inefficient and increases power consumption in mobile electronic devices like microcontrollers.
Innovation Solution
A synchronization method where the central processor decodes and sends specialized coprocessor instructions with a register tag, allowing the coprocessor to execute tasks independently while the central processor continues executing other instructions, and stalls only when the tagged result is needed, ensuring correct execution and reducing software overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polling or interrupt schemes are used for synchronization, then the central processor can coordinate with coprocessors, but software overhead increases and power consumption increases
Solution Approach 1:
The coprocessor autonomously manages its own execution status and automatically updates the status register when completion occurs, eliminating the need for continuous polling by the central processor. The system serves itself by having the coprocessor self-report completion rather than requiring external software intervention.
Solution Approach 2:
The patent replaces software-based polling and interrupt mechanisms with a hardware-based status register system. The status register is a hardware component that automatically reflects coprocessor completion state, substituting the mechanical/software overhead of polling loops and interrupt service routines with a direct hardware status indication.
2Reliability
If polling is used to check coprocessor completion, then the central processor can determine when results are ready, but execution efficiency decreases due to continuous checking
Solution Approach 1:
Instead of continuous polling, the system uses event-driven periodic action where the central processor is notified only when the coprocessor completes execution. The status register changes state periodically when completion occurs, triggering an interrupt only at those moments rather than requiring continuous checking.
Solution Approach 2:
The status register provides automatic feedback to the central processor about coprocessor completion status. When the coprocessor finishes execution, it automatically updates the status register, creating a feedback mechanism that informs the central processor of completion without requiring active querying.
3Use of energy by moving object
If interrupts are used for synchronization, then the central processor can enter low power mode, but software overhead increases due to interrupt service routines
Solution Approach 1:
The patent extracts the completion notification function from software interrupt service routines and places it in a hardware status register. The interrupt mechanism is retained only for the essential wake-up function, while the complex software handling of completion status is removed and replaced by direct hardware status checking.
4Reliability
If the central processor waits for coprocessor results, then correct execution order is maintained, but processing speed decreases
Solution Approach 1:
The system dynamically adjusts the central processor's execution flow based on the status register state. When the coprocessor is still executing, the central processor can stall or execute independent instructions. When completion occurs, the status register change dynamically triggers the resumption of dependent instructions, optimizing the balance between correctness and speed.
Data Source
AI summary
An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.