Copy-Back Cache Tracking for Redundant Controller Reliability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Process control systems with primary controllers having cache memory that does not support write-thru caching struggle to provide deterministic capture of control cycle data, hindering timely updates to parallel connected redundant secondary controllers, which is crucial for fault-tolerant industrial control systems to ensure secure backup and prevent costly downtime.

Innovation Solution

Implementing a copy-back cache flush operation to ensure all changes are written to the primary controller's main memory at the end of each control cycle, allowing for deterministic transfer of tracked changes to the secondary controller, thereby maintaining a complete and coherent set of data for secure backup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write-thru caching is used to capture changes deterministically, then data capture reliability is improved, but CPU performance deteriorates due to cache inefficiency

Engineering Contradiction:
Improvedata capture reliabilityVSAvoidCPU performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory system is segmented into cache memory and main memory, with the cache operating in copy-back mode for high-speed processing and a separate tracking buffer that monitors and records all memory accesses. This segmentation allows the cache to operate independently at high speed while the tracker deterministically captures changes, resolving the contradiction between cache performance and data capture reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A tracking buffer is introduced as an intermediary component between the cache and main memory. This buffer intercepts and records all memory write operations, providing a deterministic capture mechanism without requiring write-thru caching. The tracker acts as a mediator that enables both high-speed cache operation and reliable data capture for redundancy purposes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If cache memory without write-thru is used to improve CPU performance, then processing speed is improved, but deterministic data capture for redundancy deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoiddeterministic data capture
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The tracking buffer performs preliminary action by recording all memory write operations as they occur in the cache, before the data is eventually written back to main memory. This preliminary capture ensures that all changes are tracked deterministically in real-time, enabling reliable redundancy updates without requiring the cache to use write-thru mode, thus maintaining high processing speed while ensuring data capture reliability.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If conventional hardware memory tracker is used, then data tracking is simplified, but deterministic capture at end of control cycle fails with copy-back cache

Engineering Contradiction:
Improvetracking simplicityVSAvoiddeterministic capture
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The tracking buffer serves as an intermediary that simplifies the tracking mechanism while ensuring deterministic capture. Instead of relying on complex end-of-cycle flush operations, the tracker continuously monitors and records memory accesses in the buffer, providing a simple yet reliable mechanism that works seamlessly with copy-back cache architecture. This approach maintains tracking simplicity while achieving deterministic data capture for redundancy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9990286B1Memory tracking using copy-back cache for 1:1 device redundancy
Publication Date: 2018.06.05 HONEYWELL INTERNATIONAL INC
  • US9990286B1 patent drawing
  • US9990286B1 patent drawing
  • US9990286B1 patent drawing

AI summary

A redundant process controller arrangement includes a primary controller and parallel connected secondary controller each coupled to actuators and sensors coupled to processing equipment. The primary and secondary controllers include a main writable memory including a cache data control algorithm, central processing unit (CPU) with cache memory including cache not supporting write-thru, tracker logic coupled to a control cycle database in a tracked memory region and to a primary tracking buffer. A redundancy link is between the CPUs for passing tracked changes. The algorithm implements memory tracking using copy-back including the primary tracker logic each cycle writing tracked changes into the primary tracking buffer, and at cycle end, transferring tracked changes from the primary tracking buffer to the secondary controller over the redundancy link, and writing tracked changes to the secondary control database.